On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs

Abstract

For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices containing these flipflops. Both approaches are based on exploiting the additional storage elements that are present in slices of 7 series FPGAs. The implicit solution is to constrain floorplanning, while the explicit solution requires quite advanced and tricky HDL coding: low-level primitives must be instantiated, including LUTs in the 2-output mode. For both approaches, we describe in detail how to enable the additional register in order to save slices. Our research was aimed at designing FIR filters for digital signal processing.