A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis

Abstract

Approximate memory is a promising technology for emerging recognition, mining and vision applications. These applications require the processing of large volumes of data to achieve energy-efficiency with negligible accuracy loss. This paper proposes a multi-level approximate memory architecture based on data significance analysis. In this architecture, a memory array is divided into several separated banks with different predefined accuracy levels. A key novelty of this work is the design of a memory controller that distributes data to the memory banks according to the results of data significance analysis. When applied to a DCT (Discrete Cosine Transform) processing module, the proposed approximate memory controller can achieve over 60% power saving with onchip memory model of multiple supply voltage SRAM banks, at the cost of a marginal output PSNR (Peak Signal to Noise Ratio) degradation of 3.34 dB.