Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect

Abstract

This paper proposes a dual-clock based solution for QC-LDPC partially parallel flooded decoders. It aims at reducing memory and routing overhead, while maintaining a high degree of parallelism at processing node level. We take advantage of the high memory working frequencies with respect to the processing units, and use two clock domains: a high frequency for memory and the barrel shifter based routing network f_H, and a slower clock f_L for the processing components. The proposed technique allows us to emulate the high cost features required by increased parallelism at processing unit level - multi-port memories and multiple barrel shifters for routing -, while utilizing reduced memory and routing resources. We present FPGA implementation results for a (3,6) regular LDPC code, with a 3:1 ratio between the f_H and f_L. The results indicate a 25% throughput increase, with no memory overhead.