International Journal of Circuit Theory and Applications最新文献

{"title":"Design of Broadband Doherty Power Amplifier Based on Spoof Surface Plasmon Polaritons","authors":"Hongbo Zhang,&nbsp;Maojia Geng,&nbsp;Giovanni Crupi,&nbsp;Jialin Cai","doi":"10.1002/cta.4439","DOIUrl":"https://doi.org/10.1002/cta.4439","url":null,"abstract":"<div>\u0000 \u0000 <p>Spoof surface plasmon polariton (SSPP) is a technique for controlling and manipulating electromagnetic waves within the microwave frequency range through ultrathin corrugated metallic strips. According to current research, SSPPs are primarily used for designing passive circuits and single-ended power amplifiers (PAs). This work employs SSPP theory for the design of a broadband high-efficiency Doherty power amplifier (DPA). The input and output matching networks of the carrier power amplifier (CPA) and peak power amplifier (PPA) are designed based on SSPP structure in order to improve the back-off (BO) efficiency of the DPAs. Results of measurements indicate that the proposed height-variable SSPP-based DPA achieves a saturated output power of 41.4 dBm and a maximum efficiency of 61.1% within the frequency range of 1.6–2.2 GHz, whereas BO efficiency remains above 51.2%, demonstrating the effectiveness of the proposed techniques.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5678-5690"},"PeriodicalIF":1.6,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Latency Multikernel Polar Codes Using Approximate Processing Element","authors":"Jali Nandini,&nbsp;Pullakandam Muralidhar,&nbsp;Patri Sreehari Rao","doi":"10.1002/cta.4446","DOIUrl":"https://doi.org/10.1002/cta.4446","url":null,"abstract":"<div>\u0000 \u0000 <p>Polar codes have become increasingly popular over the last few years and are currently adopted for the control channels in 5G wireless communication systems. However, the traditional polar codes use a (2 \u0000<span></span><math>\u0000 <mo>×</mo></math> 2) binary kernel, which limits codeword lengths to powers of 2. Multikernel polar codes were proposed to provide flexibility in terms of codeword lengths and are decoded using a successive cancellation (SC) decoder. This work presents the architecture of a low-latency SC decoder based on an approximate technique, decoding 3 bits in a single clock cycle at the final stage. The processing elements of the decoder are synthesized using the Synopsys design compiler in CMOS 32-nm technology. The processing element shows an average reduction of 53% in the area and 66.5% power savings. The proposed decoder's architecture is validated by FPGA implementation for a codeword length (768,384) and a code rate of 0.5. The proposed architecture demonstrates an effective hardware reduction technique with a significant decrease in the average latency of 51% and a minimal degradation in error performance, making it suitable for video broadcasting applications in 5G communications.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5893-5902"},"PeriodicalIF":1.6,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Efficiency of Weakly Coupled Wireless High-Power Transfer Systems by Loss-Separation Strategy","authors":"Hoach The Nguyen,&nbsp;Ameena Saad Al-Sumaiti,&nbsp;Ahmad Bala Alhassan,&nbsp;Ton Duc Do","doi":"10.1002/cta.4400","DOIUrl":"https://doi.org/10.1002/cta.4400","url":null,"abstract":"<div>\u0000 \u0000 <p>In the equivalent T-model of the loosely coupled transformers, the small mutual inductance can lead to higher conducting currents, which cause high losses in the primary circuit and significantly reduce the overall transfer efficiency under weak-coupling states. To overcome this challenge, this paper proposes a strategy to separate the primary loss components from the weak-coupling stage. In the proposed strategy, a gyrator in the form of a double-resonance T-block is added just before the weak-coupling stage to improve the overall efficiency. Then, the strategy is realized by various topologies such as compensating circuits, added coils, isolated transformers, and integrated-/split- inductors/coils. Also, the optimized designs and component selection for resonance and the mathematical derivation for optimal load resistances were investigated. ANSYS comparative analyses of the topologies are presented by considering practical aspects, including component designs, power flows, transfer efficiency, resonance frequency shifting, and optimal loads. Finally, the analyses were validated using the fabricated experimental setups and demonstrated an efficiency improvement of about 5% for a case with a coupling factor of 0.1. The proposed strategy offers suggestions for industrial designs of high-power wireless battery charging systems using resonant inductive coils.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5638-5650"},"PeriodicalIF":1.6,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Connecting Equivalent Magnetic Network Considering Local Magnetic Characteristics for SPM Motors","authors":"Zhongyi Zhang,&nbsp;Bin Li,&nbsp;Xiaochen Ma,&nbsp;Guidan Li,&nbsp;Peng Gao","doi":"10.1002/cta.4448","DOIUrl":"https://doi.org/10.1002/cta.4448","url":null,"abstract":"<div>\u0000 \u0000 <p>Considering the local magnetic characteristics of surface-mounted permanent magnet (SPM) motors, the paper proposes an adaptive connecting equivalent magnetic network (ACEMN) model to accurately predict SPM motor performance. First, for modeling the magnetic field at the inclined boundary of the stator pole shoe, a diagonal hybrid permeance element covering two materials is developed. And considering the parallel magnetization of PMs, a branching calculation of the magnetomotive force source is performed inside a cross-shaped permeance of a fan-shaped mesh. Then, by analyzing the phenomenon of magnetic field line deflection at the air gap boundary, an air gap node connecting way based on adaptive conversion of connecting permeances is built. Thereby, the rotating magnetic field of the air gap can be accurately described using the different connecting permeances with variable size. To accelerate the nonlinear solution for saturated element permeability, a hybrid iterative method is used. The validity of this modeling method is verified by finite element analysis (FEA) and prototype experiments, which allows a satisfactory compromise between accuracy and calculation speed.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5989-5999"},"PeriodicalIF":1.6,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.9-V, 747-nW Capacitively Biased Diode-Based Single BJT Branch Bandgap Circuit","authors":"Kewei Hu,&nbsp;Zhong Tang,&nbsp;Zhenghao Lu,&nbsp;Nick Nianxiong Tan,&nbsp;Xiaopeng Yu","doi":"10.1002/cta.4438","DOIUrl":"https://doi.org/10.1002/cta.4438","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, a bandgap reference (BGR) circuit that combines the capacitively biased diode (CBD) structure and the proportional-to-absolute-temperature (PTAT) voltage-embedded amplifier has been proposed. In order to enhance compatibility with digital domain supply voltage and achieve low power consumption, the supply voltage of the circuit is set at \u0000<span></span><math>\u0000 <mn>0.9</mn>\u0000 <mspace></mspace>\u0000 <mi>V</mi></math>, benefiting from the fact that both the CBD structure and the PTAT-embedded amplifier can operate at sub-1 V supply voltages. The circuit generates a complementary-to-absolute-temperature (CTAT) voltage through the CBD structure. PTAT voltage is achieved by a PTAT-embedded amplifier in a unity-gain feedback configuration. The calibration of temperature coefficient (TC) is realized by applying a time-domain trimming method through an on-chip RC delay circuit. The reference clock frequency is a typical 32-kHz crystal oscillator clock frequency, enabling high versatility of the circuit. Implemented in 0.13-\u0000<span></span><math>\u0000 <mi>μ</mi></math>m CMOS, measurement results show that the proposed BGR achieves an average temperature coefficient of 28 ppm/°C over −40°C to 125°C, voltage accuracy \u0000<span></span><math>\u0000 <mo>(</mo>\u0000 <mi>σ</mi>\u0000 <mo>/</mo>\u0000 <mi>μ</mi>\u0000 <mo>)</mo></math> of 0.25<i>%</i>, power supply rejection (PSR) of \u0000<span></span><math>\u0000 <mo>−</mo>\u0000 <mn>50</mn>\u0000 <mspace></mspace>\u0000 <mtext>dB</mtext>\u0000 <mspace></mspace>\u0000 <mi>@</mi>\u0000 <mspace></mspace>\u0000 <mtext>10 Hz</mtext></math>, with an active area of \u0000<span></span><math>\u0000 <mn>0.03</mn>\u0000 <mspace></mspace>\u0000 <msup>\u0000 <mrow>\u0000 <mtext>mm</mtext>\u0000 </mrow>\u0000 <mrow>\u0000 <mn>2</mn>\u0000 </mrow>\u0000 </msup></math>, and a power consumption of \u0000<span></span><math>\u0000 <mn>747</mn>\u0000 <mspace></mspace>\u0000 <mtext>nW</mtext></math>.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5186-5196"},"PeriodicalIF":1.6,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145013287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Soft-Switching Snubber Cell Design for PWM DC-DC Boost Converters: Enhanced Load-Independent Performance","authors":"Yakup Sahin,&nbsp;Naim Suleyman Ting","doi":"10.1002/cta.4440","DOIUrl":"https://doi.org/10.1002/cta.4440","url":null,"abstract":"<div>\u0000 \u0000 <p>Soft-switching (SS) boost converters are extensively utilized in applications such as renewable energy systems, electric vehicles, and high-efficiency power supplies, as they offer reduced switching losses and enhanced overall efficiency. Zero-voltage transition (ZVT) snubber cells that used SS operation perform poorly in zero-voltage switching (ZVS) turn-off at light load, although they perform well at heavy load. This study proposes a novel SS snubber cell for the PWM-DC boost converter, ensuring excellent ZVS turn-off performance under all load conditions. The main switch is turned off with ZVS at heavy and light load, so the turn-off performance is independent of the load conditions. In addition, the main switch is switched on with ZVT, and the main diode is switched with SS. The main and auxiliary semiconductor components do not expose additional voltage. In addition, the semiconductor switches are switched on with zero-current switching (ZCS) and switched off with ZVS, whereas the auxiliary diode is switched with SS. The theoretical analysis of the converter is presented, and an experimental study is conducted to demonstrate the analysis. The proposed converter is operated with an output power of 500 W and a switching frequency of 100 kHz.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"6075-6084"},"PeriodicalIF":1.6,"publicationDate":"2025-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation and Analysis of Enhanced Performance of Elliptic Curve Cryptography Processor Over Prime Field","authors":"Md. Sazedur Rahman,&nbsp;Kalyan Kumar Halder,&nbsp;Imtiaz Ahamed Apon,&nbsp;Md. Motiur Rahman Tareq","doi":"10.1002/cta.4421","DOIUrl":"https://doi.org/10.1002/cta.4421","url":null,"abstract":"<div>\u0000 \u0000 <p>Designing an optimized performance elliptic curve cryptography (ECC) processor capable of rapid point multiplication while saving hardware resources is an essential part of system security. This study introduces the implementation of a field-programmable gate array (FPGA) design of the ECC processor (ECCP), prioritizing speed, compactness, maximum operating frequency, and resultant throughput rate in the prime field of 256-bit. The processor enables efficient point multiplication for 256 bits in the twisted Edwards25519 curve, which is vital for the strength of the Edwards curve digital signature algorithm (EdDSA). Unique architectures of hardware for different modular and group operations in the twisted Edwards curve are proposed in this work. The processor achieves modular multiplication, point addition, and doubling in only 257, 1286, and 518 clock cycles, respectively. For 256-bit keys, a point multiplication takes 0.51 ms, which operates at the highest frequency of 226.7 MHz with a cycle count of 115.2 k and a throughput of 501.9 Kbps. The implementation, executed on the Kintex-7 platform for FPGA implementation in projective coordinates, utilizes 14.7 k slices. This design demonstrates time- and throughput-efficient design by providing fast scalar multiplication while using minimum hardware resources without compromising security. The proposed ECCP on the Edwards curve's performance is improved in such a way that the device uses optimized area, time, frequency, and throughput rate. To generate a key for the ECCP and EdDSA, we simulate various operations like modular arithmetic operations, group operations, and point operations required for correct ECPM implementation on Xilinx ISE and ModelSim. Then we verify these results using the Maple tool.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5477-5497"},"PeriodicalIF":1.6,"publicationDate":"2025-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing Power Quality in EV Chargers Using Advanced Quadrature Signal Generators and AI-Driven Adaptive Filtering","authors":"Gaurav Yadav,&nbsp;Mukhtiar Singh","doi":"10.1002/cta.4424","DOIUrl":"https://doi.org/10.1002/cta.4424","url":null,"abstract":"<div>\u0000 \u0000 <p>As electric vehicle (EV) adoption grows, vehicle-to-grid (V2G) technology enables bidirectional power flow in grid-interactive EV chargers. However, maintaining consistent power quality under nonideal grid conditions remains a challenge. Traditional PI controllers struggle to reduce total harmonic distortion (THD) and adjust to dynamic grid variations. This study explores machine learning techniques, including decision trees, artificial neural networks (ANN), and linear regression, as alternatives to conventional PI controllers. Decision trees emerge as the most advantageous due to their simplicity, interpretability, and ability to handle complex, nonlinear relationships with minimal data preprocessing. While ANN captures intricate patterns, it demands more computational resources and lacks transparency. Linear regression, though efficient, struggles with complex grid behaviors. The decision tree approach allows real-time adaptive control, improving THD reduction and grid stability. Additionally, a CNISOGI filter is implemented to enhance harmonic attenuation and DC-offset rejection. The system's effectiveness is validated through Matlab/Simulink simulations and a 1.1 kW hardware prototype. The results show that integrating decision tree-based controllers with advanced filtering techniques can significantly enhance power quality, grid stability, and operational efficiency in future smart grids.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5937-5958"},"PeriodicalIF":1.6,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of No-Load Normal Vibration in Single-Sided Permanent Magnet Synchronous Linear Motors With Different End Structures","authors":"Haoran Wang,&nbsp;Lei Huang,&nbsp;Xiaomei Liu","doi":"10.1002/cta.4432","DOIUrl":"https://doi.org/10.1002/cta.4432","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper investigates the no-load normal vibrations of single-sided permanent magnet synchronous linear motors (S-PMSLMs) with different end structures, addressing a significant gap in the current literature. By employing the Maxwell stress tensor method, analyzes the harmonic orders and frequencies of the no-load normal force density are analyzed. Comparative research between the comb-type auxiliary tooth (CTAT) and conventional auxiliary tooth (C-AT) structures indicates that while the CTAT marginally increases the amplitude of the no-load normal force density, it significantly reduces harmonic amplitudes and vibration levels. The theoretical and simulation analyses are validated through no-load vibration experiments, providing valuable insights for the design optimization of S-PMSLMs, particularly beneficial for high-speed transportation systems that require high precision and reliability.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5977-5988"},"PeriodicalIF":1.6,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Three-Port Quadratic Step-Up DC–DC Converter With High Gain and Continuous Input Current","authors":"Mostafa Karimi Hajiabadi,&nbsp;Alireza Lahooti Eshkevari,&nbsp;Ali Mosallanejad,&nbsp;Ahmad Salemnia","doi":"10.1002/cta.4413","DOIUrl":"https://doi.org/10.1002/cta.4413","url":null,"abstract":"<div>\u0000 \u0000 <p>This article presents a new three-port step-up DC–DC converter with two input ports and one output terminal. This converter structure achieves a higher voltage conversion ratio and better switching device power (SDP) than its multi-input counterpart circuits. Using the “quadratic” approach to reach high voltage gains and discarding coupled inductors from the topology have avoided voltage spikes on power switches, resulting in higher efficiency compared to other hard-switched multi-input counterparts. In addition, the proposed converter can transmit power from one or both inputs to the output, from the output to the inputs, or between the inputs. Besides, common ground and continuous input current for all input ports are two distinct features of the suggested topology that most multi-input converter structures lack. This paper thoroughly explains the converter operation and confirms its performance using laboratory experiments on a 200-W hardware prototype. This new topology has been compared with existing competitors, considering several indicators. Comparative studies show that the proposed topology outperforms in terms of gain and SDP. Laboratory results validate the above achievements and exhibit that the maximum achievable efficiency by this method is 94.1%. This converter is suggested for electric vehicles and microgrid applications.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5197-5210"},"PeriodicalIF":1.6,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}