International Journal of Circuit Theory and Applications最新文献_第6页

Small-Signal Modelling of Bidirectional CLLC Converters for Onboard Charging Application in Electric Vehicles 电动汽车车载充电用双向CLLC转换器的小信号建模

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-13 DOI: 10.1002/cta.4431

Nidumolu Vijaya Anand, Yalla Naveen

{"title":"Small-Signal Modelling of Bidirectional CLLC Converters for Onboard Charging Application in Electric Vehicles","authors":"Nidumolu Vijaya Anand, Yalla Naveen","doi":"10.1002/cta.4431","DOIUrl":"https://doi.org/10.1002/cta.4431","url":null,"abstract":"<div>\u0000 \u0000 <p>A two-stage onboard battery charger with an CLLC resonant converter is a widely adopted configuration in the automotive industry. The ZVS and ZCS capability of the switching devices with high operating frequency of the CLLC converters encourages its application in various EV platforms to improve efficiency. In the literature, various authors proposed many methods to control the CLLC converters efficiently, but up to now, no simple and accurate small-signal equivalent circuit modelling is available. As dynamic networks are load-dependent, closed-loop voltage and current controllers provide more stable operations in these converters. In this paper, a detailed mathematical modelling of the CLLC converters with time domain analysis has been presented. The proposed mathematical model accurately predicts the small-signal behaviors seen in pulse-frequency-modulated (PFM) CLLC resonant converters whether the switching frequency is below, near to, or above the resonant frequency. Stable closed-loop controllers for both current and voltage loops in battery charging applications are designed and detailed. A prototype hardware is been built and the experimental results with the load variations with the designed controllers are tested and the results are been discussed in the paper.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5969-5976"},"PeriodicalIF":1.6,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Coil With All-Plane High Misalignment Tolerance for Wireless Power Transfer 一种用于无线电力传输的全平面高偏差容限线圈

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-12 DOI: 10.1002/cta.4437

Peiyao Rao, Chao Liu, Mingzhu Zhou, Yizhan Zhuang, Yiming Zhang

引用次数: 0

Radiation-Tolerant SRAM for Satellite Image Compression Systems: A Hybrid Memory Array Approach 用于卫星图像压缩系统的耐辐射SRAM：一种混合存储阵列方法

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-12 DOI: 10.1002/cta.4426

Priyanka Sharma, Vaibhav Neema, Shailesh Singh Chouhan, Nitesh Kumar Soni

{"title":"Radiation-Tolerant SRAM for Satellite Image Compression Systems: A Hybrid Memory Array Approach","authors":"Priyanka Sharma, Vaibhav Neema, Shailesh Singh Chouhan, Nitesh Kumar Soni","doi":"10.1002/cta.4426","DOIUrl":"https://doi.org/10.1002/cta.4426","url":null,"abstract":"<div>\u0000 \u0000 <p>This work is based on the design of an SRAM memory array for on board satellite image compression systems, including memory size, cost, power efficiency, and vulnerability to single event upsets (SEU). Initially, we designed a memory cell, RH_14T, specifically to mitigate the impact of SEUs. Subsequently, we incorporated RH_14T into the on-board memory array in two variations: RH_14T with minimal area overhead (RH_14T_small) and RH_14T with substantial area overhead (RH_14T_large), which have critical charges of 30.10 and 38.77 fC, respectively. Given the higher sensitivity of higher order bits compared to lower order bits in image pixels, RH_14T_small was allocated for the least significant bit (LSB) positions. RH_14_large, on the other hand, was used for the most significant bit (MSB) positions within the memory array. This configuration enhanced the array's overall area, power, and space radiation tolerance. Furthermore, the RH_14T model was bench marked against other recently introduced radiation-hardened SRAM cells and compared proposed RH_14T CC18T, RHC14T, RHMC12T, SARP12T, SRRD12T, DICE, and QUCCE12T across several critical design parameters. Notably, RH_14T's sensitive nodes can recover their original data even after radiation-induced value flips. In addition to these benefits, RH_14T also demonstrates a high static voltage noise margin and reduced read and write delays compared to most of the cells it was compared with.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5562-5578"},"PeriodicalIF":1.6,"publicationDate":"2025-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145013031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a Broadband High-Efficiency Power Amplifier Based on a Miniaturized Three-Coupled Line Structure 基于小型化三耦合线路结构的宽带高效功率放大器设计

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-12 DOI: 10.1002/cta.4428

Luyu Zhang, Zhiwei Zhang, Dengfa Zhou, Chenlu Wang, Chao Gu

引用次数: 0

Current-Mirror Based Filters With Reduced Circuit Complexity 降低电路复杂度的基于电流镜的滤波器

IF 1.8 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-09 DOI: 10.1002/cta.4430

Julia Nako, Costas Psychalinos, Shahram Minaei, Erkan Yuce

引用次数: 0

Enhanced Sliding Mode Speed Control of PMSM With Real-Time Disturbance Estimation 基于实时干扰估计的永磁同步电机增强滑模速度控制

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-09 DOI: 10.1002/cta.4427

Jingxiu Wu, Yong Zhao, Yong Kong, Qiang Liu, Lei Zhang

引用次数: 0

An Adaptive Weight Model Predictive Control Strategy for Vienna Rectifiers Under Unbalanced Loads 不平衡负载下维也纳整流器的自适应权模型预测控制策略

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-08 DOI: 10.1002/cta.4409

Zhang Sun, Weidong Jin, Fan Wu, Qi Han, Yunpu Wu

{"title":"An Adaptive Weight Model Predictive Control Strategy for Vienna Rectifiers Under Unbalanced Loads","authors":"Zhang Sun, Weidong Jin, Fan Wu, Qi Han, Yunpu Wu","doi":"10.1002/cta.4409","DOIUrl":"https://doi.org/10.1002/cta.4409","url":null,"abstract":"<div>\u0000 \u0000 <p>This study tackles the challenge of managing midpoint potential imbalance and suppressing current zero-crossing distortion in Vienna rectifiers under conditions of unbalanced load. To address this, an adaptive weight model predictive control strategy is proposed. The research begins by analyzing the interaction between maintaining midpoint potential balance and mitigating current zero-crossing distortion, taking into account influences, such as current ripple, sampling inaccuracies, and load imbalance. A prediction model is formulated to predict the behavior of the voltage vector coupling error. Using this predictive framework, a multiobjective model predictive control strategy is developed, incorporating a weight adaptive optimization technique to enhance the coordination between objectives. Experimental results validate the effectiveness of the proposed approach in controlling neutral-point potential imbalance, reducing current harmonics, and suppressing zero-crossing distortion, demonstrating its advantages over existing methods.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5228-5242"},"PeriodicalIF":1.6,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.5–5 Gb/s Wide Range, 160 fJ/Pulse Fully Integrated 13th-Order CMOS IR-UWB Transmitter for Wireless Capsule Endoscopy Systems 用于无线胶囊内窥镜系统的0.5 ~ 5gb /s宽范围、160 fJ/脉冲全集成13阶CMOS IR-UWB发射机

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-05 DOI: 10.1002/cta.4379

Naga Ganesh Akuri, Kunal Kumar, Sandeep Kumar, K. S. Nikhil, Hanjung Song

{"title":"A 0.5–5 Gb/s Wide Range, 160 fJ/Pulse Fully Integrated 13th-Order CMOS IR-UWB Transmitter for Wireless Capsule Endoscopy Systems","authors":"Naga Ganesh Akuri, Kunal Kumar, Sandeep Kumar, K. S. Nikhil, Hanjung Song","doi":"10.1002/cta.4379","DOIUrl":"https://doi.org/10.1002/cta.4379","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper proposes a novel technique based fully integrated 13th-order derivative CMOS impulse-radio ultrawideband (IR-UWB) transmitter with wide range of adaptive data rates for wireless capsule endoscopy systems (WCE). The proposed IR-UWB transmitter involves BPSK modulator-integrated RF power amplifier (PA) approach for WCE in first time as per author's best knowledge. The CMOS BPSK modulator with resonator technique generates 13th-order Modulated Gaussian pulse without the pulse generator. It has a peak-to-peak value of 25 mV and PSD level of −72.60 dBm/MHz, data rate variability from 500 Mbps to 5 Gbps. The BPSK modulator with resonator is designed by time constant analysis in first time. In addition, a proposed CMOS PA is designed using four stacked transistors, which achieves a high output power as well as high efficiency for entire frequency band of operation from 3 to 16 GHz and wide impedance matching. The PA achieved an excellent gain of 16.55 dB with gain ripple of 0.25 dB only. Moreover, the PA achieved the saturated output power of 18.2 to 19.3 dBm with OP1dB of 15.96 to 16.72 dBm across entire bandwidth. Without violating FCC guidelines, PA strengths both peak-to-peak values, and PSD level of BPSK modulated signal to 80 mV and −46.42 dBm/MHz. An IR-UWB transmitter has been implemented and fabricated using 65-nm CMOS Process, which consumes of only 160 fJ/pulse for generating Gaussian pulses order ranging from third-order to more than 13th-order at various data rates.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5155-5170"},"PeriodicalIF":1.6,"publicationDate":"2025-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Three-Port Bidirectional DC–DC Converter for Application in Renewable Energy Systems 三端口双向DC-DC变换器在可再生能源系统中的应用

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-05 DOI: 10.1002/cta.4420

Juliana Carvalho de Alencar, Menaouar Berrehil El Kattel, Gabriel José Oliveira Pinheiro, Grover Victor Torrico-Bascopé, René Pastor Torrico-Bascopé

{"title":"Three-Port Bidirectional DC–DC Converter for Application in Renewable Energy Systems","authors":"Juliana Carvalho de Alencar, Menaouar Berrehil El Kattel, Gabriel José Oliveira Pinheiro, Grover Victor Torrico-Bascopé, René Pastor Torrico-Bascopé","doi":"10.1002/cta.4420","DOIUrl":"https://doi.org/10.1002/cta.4420","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper proposes a new three-port bidirectional DC–DC converter designed for integration into photovoltaic systems with battery energy storage. The proposed topology features three ports: two for power supply (one powered by batteries and the other by photovoltaic panels) and a third for the load. Due to its bidirectional characteristics, this converter facilitates power flow both from the batteries and/or photovoltaic panels to the load, as well as from the photovoltaic panels to the batteries. The converter operates in open loop, and this paper presents qualitative and quantitative analyses of the converter operating in continuous conduction mode (CCM) for two power flow scenarios. Additionally, an illustrative design is detailed for a nominal power of 1.5 kW, a switching frequency of 30 kHz, a battery voltage of 48 V, a photovoltaic panel voltage of 142 V, and a load bus voltage of 250 V. The theoretical analysis is validated through experimental results. Some of the main highlights include operating the inductor at twice the switching frequency, significantly reducing both the inductor's size and the input current ripple. Furthermore, the optimal battery current ripple occurs at a duty cycle close to 50%, where it is practically zero. The converter efficiency was analyzed in all power flow scenarios at various operating points, reaching up to 97.33%. Furthermore, a supplementary video showcasing its functionality is included with this manuscript.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5211-5227"},"PeriodicalIF":1.6,"publicationDate":"2025-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pipeline ShiftAddNet: An FPGA-Based CNN Implementation With Low Hardware Consumption Targeting Constrained Devices 流水线ShiftAddNet：一种基于fpga的低硬件消耗CNN实现

IF 1.6 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2025-01-02 DOI: 10.1002/cta.4419

Wei-Pau Kiat, Wai Kong Lee, Hung-Khoon Tan, Hui-Fuang Ng

{"title":"Pipeline ShiftAddNet: An FPGA-Based CNN Implementation With Low Hardware Consumption Targeting Constrained Devices","authors":"Wei-Pau Kiat, Wai Kong Lee, Hung-Khoon Tan, Hui-Fuang Ng","doi":"10.1002/cta.4419","DOIUrl":"https://doi.org/10.1002/cta.4419","url":null,"abstract":"<div>\u0000 \u0000 <p>ShiftAddNet is a recently proposed multiplier-less CNN that replaces conventional multiplication with cheaper shift and add operations, which makes it suitable for hardware implementation. In this paper, we present the first implementation of ShiftAddNet FPGA inference core, which achieves low area consumption and fast computation. ShiftAddNet combined the convolutional layer of the DeepShift-PS (denoted as Shift-Accumulate, <i>sac</i>) and AdderNet (denoted as Add-Accumulate, <i>aac</i>) into a single computational stage. Due to this reason, there are data dependencies between the <i>sac</i> and <i>aac</i>, which prohibits them from being executed in parallel, resulting in \u0000<span></span><math>\u0000 <mn>2</mn>\u0000 <mo>×</mo></math> more operations compared to other multiplier-less CNNs like DeepShift-PS and AdderNet. To overcome this performance bottleneck, we proposed a novel technique to allow pipeline processing between <i>sac</i> and <i>aac</i>, effectively reducing the latency. The proposed ShiftAddNet-18 was evaluated on a small ResNet-18, achieving 11.37 ms of latency per image, which is \u0000<span></span><math>\u0000 <mo>∼</mo></math>69.21% faster than the original version that takes 19.24 ms. On a denser network, the proposed pipeline ShiftAddNet-101 requires only 61.92 ms as compared to the original version of 98.85 ms, showing a latency reduction of \u0000<span></span><math>\u0000 <mo>∼</mo></math>37.1%. Compared to the state-of-the-art multiplier-less CNN core (e.g., AdderNet), our work is 20% slower in latency but provides higher accuracy and consumes \u0000<span></span><math>\u0000 <mn>2.2</mn>\u0000 <mo>×</mo></math> less DSP.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5538-5547"},"PeriodicalIF":1.6,"publicationDate":"2025-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0