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International Journal of Circuit Theory and Applications最新文献

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Multi-band pass negative group delay circuit with low insertion loss 低插入损耗的多波段负群组延迟电路
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-22 DOI: 10.1002/cta.4177
Niannan Chang, Aixia Yuan, Ying Wang, Junzheng Liu
{"title":"Multi-band pass negative group delay circuit with low insertion loss","authors":"Niannan Chang,&nbsp;Aixia Yuan,&nbsp;Ying Wang,&nbsp;Junzheng Liu","doi":"10.1002/cta.4177","DOIUrl":"10.1002/cta.4177","url":null,"abstract":"<p>A novel multi-band pass negative group delay circuit has been designed and proposed. The circuit consists of three types of components: capacitance, inductance, and resistance. An <i>n</i>-order bandpass negative group delay circuit was analyzed and presented, and taking a three-frequency bandpass negative group delay circuit as an example, the influence of different component values on the circuit group delay and insertion loss was analyzed. The actual test results of this circuit are consistent with the simulation results, and it can achieve the function of a multi-bandpass circuit. In actual testing, the circuit frequencies with negative group delay are 49, 82, and 102 MHz, with corresponding group delay values of −2.177, −2.058, and −1.903 ns and corresponding insertion loss values of −5.810, −5.835, and −5.866 dB.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1292-1301"},"PeriodicalIF":1.8,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sliding mode disturbance compensated speed control for PMSM based on an advanced reaching law 基于先进达到律的 PMSM 滑动模式扰动补偿速度控制
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-22 DOI: 10.1002/cta.4185
Chengming Chen, Zhizhong Xie, Xuan Wang, Zhengling Lei, Chunxia Shangguan
{"title":"Sliding mode disturbance compensated speed control for PMSM based on an advanced reaching law","authors":"Chengming Chen,&nbsp;Zhizhong Xie,&nbsp;Xuan Wang,&nbsp;Zhengling Lei,&nbsp;Chunxia Shangguan","doi":"10.1002/cta.4185","DOIUrl":"10.1002/cta.4185","url":null,"abstract":"<p>Addressing the sensitivity of permanent magnet synchronous motors to external disturbances, a novel sliding mode control (NSMC) strategy is proposed to suppress sliding mode jitter and enhance speed regulation performance. First, an advanced nonsingular fast terminal sliding mode (ANFTSM) surface and a new adaptive power rate reaching law (NAPRRL) were developed. A new switching function replaces the conventional sign function to enhance the system's disturbance immunity and dynamic response speed. Then, the system's anti-interference performance was further enhanced by introducing an improved novel sliding mode observer (INSMO) for feedback compensation of the aggregate disturbance. Finally, MATLAB/Simulink simulations and experimental validations demonstrate that the NSMC control strategy exhibits superior performance in both the start-up response and load disturbance phases, with enhanced dither resistance, rapid dynamic response, and disturbance suppression capabilities.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1541-1555"},"PeriodicalIF":1.8,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High gain bipolar converter with reduced input current ripple for fuel cell integrated DC microgrid 用于燃料电池集成直流微电网的高增益双极转换器，可降低输入电流纹波
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-18 DOI: 10.1002/cta.4174
Ashish Prajapati, Kalpana Chaudhary
{"title":"High gain bipolar converter with reduced input current ripple for fuel cell integrated DC microgrid","authors":"Ashish Prajapati,&nbsp;Kalpana Chaudhary","doi":"10.1002/cta.4174","DOIUrl":"10.1002/cta.4174","url":null,"abstract":"<p>The key characteristics of a DC-DC converter for a fuel cell (FC) application include higher voltage gain for DC-link voltage, the continuous and ripple-free source current that is beneficial for FC. This paper proposes a high-gain DC-DC converter with continuous and ripple-free input current. The proposed converter is suitable for integrating fuel cell and photovoltaic (PV) power into an isolated DC microgrid. Modified boost converter with an intermediate capacitor integrated with the cuk converter to achieve high voltage gain and low voltage stress across switches, which also reduces the reverse recovery problem of diodes. A prototype of a 1 kW converter is designed, developed, and analyzed to verify its working principle. The simulation and experimental results for high gain 40/400 V and 1 kW load power, with a DC microgrid of 400 V connected to the proposed converter, are in good harmony and are conforming to the theoretical analysis. The maximum obtained converter efficiency is 96.13%.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1512-1540"},"PeriodicalIF":1.8,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a multi-octave high-efficiency power amplifier employing a modified continuous class-GF mode 设计采用改进型连续 GF 类模式的多倍频程高效功率放大器
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-17 DOI: 10.1002/cta.4194
Haipeng Zhu, Zhiwei Zhang, Xuefei Xuan, Chenlu Wang, Luyu Zhang, Chao Gu
{"title":"Design of a multi-octave high-efficiency power amplifier employing a modified continuous class-GF mode","authors":"Haipeng Zhu,&nbsp;Zhiwei Zhang,&nbsp;Xuefei Xuan,&nbsp;Chenlu Wang,&nbsp;Luyu Zhang,&nbsp;Chao Gu","doi":"10.1002/cta.4194","DOIUrl":"10.1002/cta.4194","url":null,"abstract":"<p>This paper introduces a modified continuous mode class-GF power amplifier (PA) incorporating a phase shift parameter to modify the drain voltage waveform. This modification significantly boosts the overlap area between the fundamental impedance and the second harmonic impedance, thereby providing increased flexibility in designing a broadband matching network. Additionally, a straightforward modified coupler network is proposed to effectively accommodate the expanded impedance design space. Experimental validation was conducted with a PA operating within the frequency range of 0.5–3.5 GHz. The results affirm the efficacy of the proposed approach, with the saturated output power ranging from 40.0 to 42.5 dBm, accompanied by a gain exceeding 10 dB. Furthermore, a remarkable drain efficiency ranging from 59% to 76.2% is achieved within the targeted frequency band.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1342-1353"},"PeriodicalIF":1.8,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel multimode constant magnetizing current battery equalizer with few sensors in electric vehicles 新型多模恒定磁化电流电池均衡器，传感器数量少，适用于电动汽车
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-17 DOI: 10.1002/cta.4165
Runmin Zou, Wenqi Zhou, Ji Wang
{"title":"A novel multimode constant magnetizing current battery equalizer with few sensors in electric vehicles","authors":"Runmin Zou,&nbsp;Wenqi Zhou,&nbsp;Ji Wang","doi":"10.1002/cta.4165","DOIUrl":"10.1002/cta.4165","url":null,"abstract":"<p>The conventional automatic battery equalizer is characterized by its low cost in batter management system. However, its effectiveness is limited by the absence of signal feedback, leading to inadequate self-regulation and protection of the topology. In this paper, an equalizer with constant magnetizing current is proposed. By adjusting the duty cycle of the MOSFETs, the magnetizing current can be flexibly controlled, which greatly improves the equalization rate and safety. The topology has multiple modes such as cell to cell (C2C), cell to string (C2S), and string to string (S2S). A creative signal sampling method is designed to obtain the cell voltage and magnetizing current with few sensors. And a novel balancing strategy is proposed, which can achieve wonderful accuracy of equalization at any initial voltage distribution.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 4","pages":"2227-2248"},"PeriodicalIF":1.8,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance analysis of fractional-order modified SRF PLL under grid abnormalities 电网异常情况下分数阶修正 SRF PLL 的性能分析
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-17 DOI: 10.1002/cta.4161
Oinam Lotika Devi, Alka Singh
{"title":"Performance analysis of fractional-order modified SRF PLL under grid abnormalities","authors":"Oinam Lotika Devi,&nbsp;Alka Singh","doi":"10.1002/cta.4161","DOIUrl":"10.1002/cta.4161","url":null,"abstract":"<p>This article proposes two different structures of fractional-order modified synchronous reference frame phase-locked loop (MSRF PLL) and discusses their performance under different grid abnormalities. Phase-locked loop (PLL) is a type of closed-loop feedback control system that ensures phase and frequency coherence between its input and output signals. The basic synchronous reference frame phase-locked loop (SRF-PLL) is a conventional synchronization technique that is frequently employed in grid-connected systems for power electronic converters. The SRF-PLL offers rapid and precise phase/frequency detection under ideal grid environments. However, its performance is severely hampered under unbalanced and distorted grid environments. This paper discusses two new configurations of fractional-order (FO) modified SRF (MSRF), one with fractional order only in additional low-pass filter of first order (FO-LP) and another fractional order in both first-order low-pass filter and PI (FO-LPFO-PI) of MSRF. These controllers are assembled using FOs “<i>a</i>” and “<i>b</i>” with limits as 0 &lt; <i>a</i> &lt; 2 and 0 &lt; <i>b</i> &lt; 2. The performance analysis of proposed FO MSRFs is done under grid abnormalities like voltage sag and swell, polluted grid supply, frequency change, phase change, and variables for dc offset. The outcomes of simulation are acquired using FO modeling and control (FOMCON) toolbox for MATLAB/SIMULINK, and the experimental results are validated with simulation results. A fair comparison among the MSRF-PLL, FO-LP MSRF-PLL, and FO-LPFO-PI MSRF-PLL is also depicted during grid abnormalities.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1491-1511"},"PeriodicalIF":1.8,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and optimization of 30 kW CLLLC resonant converter for vehicle-to-grid applications 设计和优化用于车联网应用的 30 千瓦 CLLLC 谐振转换器
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-16 DOI: 10.1002/cta.4181
Donghao Tian, Yu Tang, Zhe Shi
{"title":"Design and optimization of 30 kW CLLLC resonant converter for vehicle-to-grid applications","authors":"Donghao Tian,&nbsp;Yu Tang,&nbsp;Zhe Shi","doi":"10.1002/cta.4181","DOIUrl":"10.1002/cta.4181","url":null,"abstract":"<p>The CLLLC resonant converter is a promising technology for electric vehicles and microgrids due to its ability to operate bidirectionally. This article presents a design of a bidirectional CLLLC resonant converter that is applied in the vehicle-to-grid (V2G). The battery side of the converter uses a two-channel parallel structure to enhance its efficiency and reliability. In contrast, the DC-bus side uses a transformer series structure to obtain the benefits of passive current sharing on the secondary side and reduce the transformer turns ratio. By utilizing the proposed design method, the converter can achieve a wide input and output voltage range, high efficiency, and high power density. The article analyzes the working principle of the converter and explains the design process, which includes the transformer turns ratio, magnetizing inductance, and resonance parameters. Finally, an experimental prototype is produced to verify the theory's validity and the design's feasibility. The prototype has a DC-bus side voltage of 660–860 V, a battery side voltage of 250–500 V, and a maximum power output of 30 kW. The peak efficiency of the prototype is 98.2<i>%</i>, and its power density can reach up to 8 kW/L.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1593-1607"},"PeriodicalIF":1.8,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 40.3–50.5 GHz locking range transformer-based injection-locked frequency divider utilizing a high third harmonic rejection buffer 利用高三次谐波抑制缓冲器的 40.3-50.5 GHz 锁定范围变压器式注入锁定分频器
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-15 DOI: 10.1002/cta.4189
Xinsheng Wang, Yanhong Song, Xiyue Wang
{"title":"A 40.3–50.5 GHz locking range transformer-based injection-locked frequency divider utilizing a high third harmonic rejection buffer","authors":"Xinsheng Wang,&nbsp;Yanhong Song,&nbsp;Xiyue Wang","doi":"10.1002/cta.4189","DOIUrl":"10.1002/cta.4189","url":null,"abstract":"<p>Injection-locked dividers feature ultrahigh operating frequency, low power consumption, and low phase noise, making them suitable for Q-band phase-locked loop. This paper presents a transformer-based divide-by-4 injection locking frequency divider with a high third harmonic rejection buffer based on 40-nm CMOS technology. Employing a fourth-order transformer resonator enhances the third-order harmonic amplitude, increasing the injection efficiency and expanding the locking range. The proposed high third harmonic rejection buffer using a source degeneration inductor can effectively suppress the output of the third harmonic caused by the resonator, ultimately yielding a clean fundamental frequency signal. Simulation results demonstrate that the proposed divide-by-4 injection-locked frequency divider (ILFD) achieves a locking range of 10.2 GHz (from 40.3 to 50.5 GHz) with 0 dBm input signal. The core divide-by-4 ILFD circuit consumes 4.6 mW power with a 0.9 V supply and occupies an area of 0.026 mm<sup>2</sup>.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1184-1198"},"PeriodicalIF":1.8,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141646104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient three-phase two-level voltage source inverter with the suppression of the dead time effect 抑制死区时间效应的高效三相两电平电压源逆变器
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-11 DOI: 10.1002/cta.4180
Qiang Wang, Xiang Gong, Youzheng Wang
{"title":"An efficient three-phase two-level voltage source inverter with the suppression of the dead time effect","authors":"Qiang Wang,&nbsp;Xiang Gong,&nbsp;Youzheng Wang","doi":"10.1002/cta.4180","DOIUrl":"10.1002/cta.4180","url":null,"abstract":"<p>The paper carries out the research on a novel two-level voltage source inverter to further improve the output power quality of the inverter under the premise of efficient operation. Main switches can realize zero-voltage switching in a wide load range to ensure the efficient operation of the designed inverter. Total harmonic distortion (THD) of the output current at low output frequencies can be improved by the modification of resonant tanks in the designed inverter. In the dead time, the modified resonant tanks can result in a shorter duration of nonlinear changes in the output phase voltage at lower load current, which is beneficial for reducing the output voltage error caused by dead time. The improved power quality at low output frequencies is conductive to the use of the designed inverter in the drive system of the low-speed AC motor. The paper expounds every operating status during a switching period. The experiment manifests that switches realize soft switching. The efficiency of the designed inverter reaches 98.6% at rated operation state, which is 0.3% and 0.5% more than that of two comparison objects, respectively. Moreover, when the output frequency reduces to 5 Hz, the THD of the output current is only 2%, which is also less than that of comparison objects. Hence, the designed inverter has advantages in the efficiency and the output power quality.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1474-1490"},"PeriodicalIF":1.8,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141610813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications 使用有源电感器的宽调谐范围 CMOS 差分环形 VCO，适用于无线应用
IF 1.8 3区 工程技术
International Journal of Circuit Theory and Applications Pub Date : 2024-07-11 DOI: 10.1002/cta.4155
Mahdi Alijani, Mohammadmahdi Javanmardi, Adib Abrishamifar
{"title":"A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications","authors":"Mahdi Alijani,&nbsp;Mohammadmahdi Javanmardi,&nbsp;Adib Abrishamifar","doi":"10.1002/cta.4155","DOIUrl":"10.1002/cta.4155","url":null,"abstract":"<p>A differential ring voltage-controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low-noise and high-quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180-nm CMOS technology with a 1.8-V voltage source (<i>V</i><sub>DD</sub>). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm<sup>2</sup>. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 3","pages":"1171-1183"},"PeriodicalIF":1.8,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141610812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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