K. Ashwin, K. Nakul Narayanan, L. Umanand, B. Subba Reddy
{"title":"A Current-Fed Switched Capacitor Inverter With Voltage Boosting, Reduced Harmonic Distortion, and Minimal Device Count","authors":"K. Ashwin, K. Nakul Narayanan, L. Umanand, B. Subba Reddy","doi":"10.1002/cta.4386","DOIUrl":"https://doi.org/10.1002/cta.4386","url":null,"abstract":"<div>\u0000 \u0000 <p>DC–AC inverters are an important set of power converters when it comes to integration of the renewable energy resources in to the AC grid or to local AC loads. The multilevel inverters (MLIs) are a common and popular choice for such applications. However, MLIs require many switching devices for higher number of voltage levels, multiple isolated DC sources, need for additional charge-balancing circuits for the DC-link capacitor, and unequal voltage stress in the devices at higher power levels. Switched capacitor–based inverters are emerging as a popular alternative to the conventional MLIs that do provide inherent charge balancing, reduced device stress, output voltage–boosting capability, and highly compact converters. This work proposes such a current-fed DC–AC switched capacitor converter (SCC). This converter offers advantages such as reduced count of switched capacitors and power devices, elimination of load-side filtering elements, reduced switching ripple in output voltage due to inherent interleaving, reduced voltage and current total harmonic distortion (THD), and lower ratings of the switched capacitors. An adaptive hysteresis control scheme is used to track the voltage across the switched capacitors to a desired sinusoidal reference. The overall control architecture is straightforward to implement, and the switching architecture uses overlapping logic to prevent interrupting the input current. The work includes a complete analysis and design procedure. A 500-W laboratory prototype of the proposed converter is built, with the control architecture implemented using the TMS320F28379D microcontroller. Simulation results are verified with experimental outcomes.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5007-5026"},"PeriodicalIF":1.6,"publicationDate":"2024-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA-Based Resource-Optimal Approximate Multiplier for Error-Resilient Applications","authors":"Burhan Khurshid","doi":"10.1002/cta.4398","DOIUrl":"https://doi.org/10.1002/cta.4398","url":null,"abstract":"<div>\u0000 \u0000 <p>Arithmetic units inspired by approximate computations have seen a significant development in error-resilient applications, wherein accuracy can be traded off for enhanced performance. Most of the existing literature pertaining to approximate computations targets ASIC platforms. In this paper, we focus on exploiting the features of approximate computation to design efficient digital hardware for FPGA platforms. Specifically, we propose an FPGA implementation of an approximate multiplier unit based on the CORDIC algorithm. Contemporary FPGA-based approximate multiplier implementations report a lot of compromise in accuracy and a relatively higher implementation cost in terms of utilized resources, timing, and energy. We conduct a detailed Pareto analysis to determine the number of optimal computing stages for the proposed CORDIC-based approximate multiplier that justifies the accuracy-performance trade-offs. More importantly, we focus on the optimal logic distribution of the proposed multiplier circuit by restructuring the top-level Boolean network and translating it into a circuit netlist that can be efficiently mapped onto the inherent FPGA fabric of LUTs and Carry4 primitives. Our CORDIC-based implementations significantly improve the accuracy metrics while maintaining a suitable performance trade-off. The efficacy of our proposed multiplier is tested using two image-processing applications, namely, image blending and image smoothening. The obtained results show a substantial improvement over the existing state-of-the-art approximate multipliers.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5518-5537"},"PeriodicalIF":1.6,"publicationDate":"2024-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ningzhi Jin, Jiaowei Hou, Jiaxin Jiang, Jing Yang, Dongyang Sun
{"title":"Quasi-Z-Source Cascaded Multilevel Inverter With Master-Division Control for Photovoltaic Grid Connection","authors":"Ningzhi Jin, Jiaowei Hou, Jiaxin Jiang, Jing Yang, Dongyang Sun","doi":"10.1002/cta.4388","DOIUrl":"https://doi.org/10.1002/cta.4388","url":null,"abstract":"<div>\u0000 \u0000 <p>The quasi-Z-source cascaded multilevel inverter (qZS-CMI) can achieve the boost function through the shoot-through state without the requirement of an additional DC boost circuit. Thus, the efficiency of the system is improved, and each power module can be controlled independently, which makes it more suitable for distributed photovoltaic power generation systems. This paper proposes a multi-carrier phase-shifted PWM (MPSPWM) that inserts a shoot-through signal at the switching moment, in order to address the high switching frequency problem caused by simple boost modulation in qZS-CMI. In order to improve the dynamic response of the system and reduce the grid-connected current distortion of qZS-CMI, this paper proposes a master-division grid-connected control strategy. The DC-link voltage division controllers use the sliding mode control to achieve DC-link voltage stabilization, and the grid-connected current master controller adopts an improved deadbeat control to achieve fast tracking of grid-connected current. When the output power of PV arrays is inconsistent, the differential power allocation between modules is realized by setting the module power allocation factor. Finally, the effectiveness and feasibility of the above theory are verified by three-module cascaded qZS-CMI simulation and experiment.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5255-5274"},"PeriodicalIF":1.6,"publicationDate":"2024-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Brain-Like Biomimetic Circuit Design Based on Memristor","authors":"Lixin Liu","doi":"10.1002/cta.4399","DOIUrl":"https://doi.org/10.1002/cta.4399","url":null,"abstract":"<div>\u0000 \u0000 <p>In this work, inspired by the neural mechanisms of the human brain, a brain-like biomimetic circuit based on visual information processing is proposed. The circuit is mainly composed of test module, cognitive module, categorization module, and output module. The cognitive module mimics the function of memory neurons in the brain, generating memory potentials to store information while receiving visual information stimuli. The categorization module mimics the function of the visual cortex, enabling the conversion from memory to action. I verified the feasibility of this circuit for information processing using LTspice. This study provides new ideas and insights for the future development of visual information processing technology for electronic products.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5042-5053"},"PeriodicalIF":1.6,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Grid-Forming Interlinking Converter With Fault-Ride-Through Capability in Islanded Hybrid AC/DC Microgrids","authors":"Xia Shen, Chao Shen, Feng Zhao, Wen Huang","doi":"10.1002/cta.4394","DOIUrl":"https://doi.org/10.1002/cta.4394","url":null,"abstract":"<div>\u0000 \u0000 <p>With the expansion of hybrid AC/DC microgrids (MGs), the AC and DC subgrids should be able to maintain interconnection through interlinking converter (IC) under short-circuit faults to avoid the system instability caused by power mutation. Conventional IC control methods have given insights into the current restraining between two subgrids but neglect the transient voltage/frequency support requirement, especially under islanded operation mode. This paper proposes a grid-forming IC control with fault-ride-through (FRT) capability. An <i>f</i><sub>n</sub>-<i>P</i><sub>ic</sub>-<i>V</i><sub>dc</sub> control architecture is presented to regulate power exchanges among AC and DC subgrids with solid AC bus voltage supports under the premise of DC voltage stable. Additionally, the Lyapunov large disturbance stability equation is established, and the safe operating boundaries of key parameters are described based on the Takagi–Sugeno (TS) model criterion. It is revealed that within certain range, the proper DC voltage feedback control parameters in IC could enhance the system stability and the power support capability of DC subgrid to the AC side. Finally, comparative case studies are conducted to validate effectiveness of the proposed control strategy.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5410-5421"},"PeriodicalIF":1.6,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chentao Ma, Xiaoquan Zhu, Ziwen Chen, Jintao Hou, Bo Zhang
{"title":"Analysis and Modeling of Fractional Order LC Series Resonant Boost Converter Based on Fractional Calculus and Laplace Transform","authors":"Chentao Ma, Xiaoquan Zhu, Ziwen Chen, Jintao Hou, Bo Zhang","doi":"10.1002/cta.4396","DOIUrl":"https://doi.org/10.1002/cta.4396","url":null,"abstract":"<div>\u0000 \u0000 <p>Based on the fractional-order (FO) characteristics of inductors and capacitors, many basic PWM DC–DC converters are defined and modeled by FO calculus in previous studies, but the research of FO resonant dc converters is still in its early stage. Therefore, this paper adopts FO calculus and Laplace transform to model and analyze a ZCS boost converter with an LC resonant tank, which mainly focuses on the influence of the FO component on the soft switching characteristics, converter efficiency, and output voltage gain of this isolated dc converter. This paper extends the topology to the fractional order domain and conducts FO modeling. The order of the resonant inductor and capacitor will affect the amplitude/phase of the resonant current and then affect the converter ZCS characteristic. The analysis demonstrates that the reduction of FOI and FOC order is not conducive to the ZCS of switching devices and converter efficiency. Based on the voltage and current relationship of the FO LC resonant tank, a parameter design guideline is presented. Numerical tools are used to solve the FO output voltage gain and draw the gain curve. And the order of FOI and FOC provides new flexibility for the converter output gain and soft switching design. Finally, simulations and a 360 W hardware experimental prototype are conducted to verify the accuracy and effectiveness of theoretical analysis.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5027-5041"},"PeriodicalIF":1.6,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Scalable Delay-Expanding Technique for Low-Area On-Chip Power-On Reset Circuits","authors":"Hamid Sadat Mansoury, Saeed Saeedi, Mojtaba Atarodi","doi":"10.1002/cta.4380","DOIUrl":"https://doi.org/10.1002/cta.4380","url":null,"abstract":"<div>\u0000 \u0000 <p>A scalable structure is presented and analyzed that can provide delays in a wide range (microseconds to minutes) for the power-on reset circuit. The proposed structure enables the implementation of these delays entirely on-chip through the utilization of a provisional oscillator and a set of flip-flops. The optimal number of flip-flops can be determined through an area optimization process. The proposed power-on reset circuit thresholds demonstrate the process, voltage, temperature (PVT) tolerance, facilitated by the use of resistors of the same type. Notably, the thresholds and provided delay for this circuit are supply-rise-time independent. The structure has been implemented in a 0.18-μm CMOS technology, occupying an active area of 48 × 40 μm<sup>2</sup>.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5507-5517"},"PeriodicalIF":1.6,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Step-Up Isolated Multi-Input Converter Based on Three-Winding Coupled Inductor and Quasi-Z-Source for Excellent Voltage Gain With Independent Control and Expandability","authors":"Chih-Lung Shen, You-Xun Xie, Shu-Yuan Fan, Ho-Teng Huang, Zhen-Yuan Xie","doi":"10.1002/cta.4389","DOIUrl":"https://doi.org/10.1002/cta.4389","url":null,"abstract":"<div>\u0000 \u0000 <p>This article introduces a high step-up isolated multi-input converter (HSIMIC), which utilizes a three-winding coupled inductor and a quasi-Z-source to obtain an extra-high voltage gain and to feature galvanic isolation. The HSIMIC only requires a minimum count of active switches. In HSIMIC, diodes have zero current switching (ZCS) features at turn-off, and leakage energy can be recycled. Based on the configuration of HSIMIC, the input sources can be processed simultaneously or individually. Even if either of the input sources is interrupted, the converter can still function and maintain the high step-up characteristic. In addition, the input port number can be easily extended to deal with more clean energy sources. The converter operation principle, theoretical analysis, essential parameter design, and simulations are carried out. A 400-W prototype is built and then tested to verify the theoretical analysis and validate the proposed HSIMIC.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 8","pages":"4526-4540"},"PeriodicalIF":1.6,"publicationDate":"2024-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144767575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Suyash Shrivastava, Pydi Ganga Bahubalindruni, Nishtha Wadhwa, Pedro Barquinha
{"title":"A Wide Range Duty-Cycle PWM Generator Using Oxide-TFTs on a Flexible Substrate","authors":"Suyash Shrivastava, Pydi Ganga Bahubalindruni, Nishtha Wadhwa, Pedro Barquinha","doi":"10.1002/cta.4390","DOIUrl":"https://doi.org/10.1002/cta.4390","url":null,"abstract":"<div>\u0000 \u0000 <p>This work presents an experimental characterization of a novel clocked regenerative comparator with oxide TFT (a-IGZO) technology on a flexible substrate. The circuit functionality is demonstrated as a wide range duty-cycle PWM signal generator with a triangular input signal. The regenerative latch in the comparator is implemented with diode-load–based inverters. The proposed circuit has shown a linear variation in the duty-cycle from 12% to 84%, when the reference voltage (\u0000<span></span><math>\u0000 <msub>\u0000 <mrow>\u0000 <mi>V</mi>\u0000 </mrow>\u0000 <mrow>\u0000 <mi>r</mi>\u0000 <mi>e</mi>\u0000 <mi>f</mi>\u0000 </mrow>\u0000 </msub></math>) is varied from 0.5 to 3.3 V, respectively, in the clocked comparator. Further, a reliable operation is observed up to an input signal frequency of 2 kHz at a supply voltage of 4 V, with a power dissipation of 20 \u0000<span></span><math>\u0000 <mi>μ</mi></math> W. This circuit would find potential applications in wearable bio-medical and neuromorphic computational systems.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 8","pages":"4837-4841"},"PeriodicalIF":1.6,"publicationDate":"2024-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144767577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis and Design of Stacked Coupled Inductor Quadratic Boost Converter With a Lossless Snubber Cell","authors":"Yavuz Koç, Yaşar Birbir, Erdoğan Özel","doi":"10.1002/cta.4393","DOIUrl":"https://doi.org/10.1002/cta.4393","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper introduces the stacked coupled inductor quadratic boost converter with an inductorless, passive lossless snubber cell suited for high step-up applications with various microgrids. Some design constraints can be selected from the voltage gain techniques of the high step-up converters to obtain the solution of improvement performance of converter. The proposed converter utilizes quadratic boost converter and coupled inductor to attain high voltage gain beyond the voltage multiplier/lift cells. In this proposed converter, the use of a stacked coupled inductor type introduces the leakage inductor to snubber cell as an inductor without using an extra inductor in proposed snubber cell. Thus, a regenerative snubber cell is used to achieve a high system efficiency. Compared with earlier counterparts, the solution of attaining a high voltage gain in the proposed converter and passive lossless snubber cell leads to an increase in the converter's performance, reliability, and robustness. The theoretical expectations are supported by simulations and verified by experimental results obtained by implementing a 300-V, 120-W prototype.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 8","pages":"4541-4559"},"PeriodicalIF":1.6,"publicationDate":"2024-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144767576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}