A Scalable Delay-Expanding Technique for Low-Area On-Chip Power-On Reset Circuits

A scalable structure is presented and analyzed that can provide delays in a wide range (microseconds to minutes) for the power-on reset circuit. The proposed structure enables the implementation of these delays entirely on-chip through the utilization of a provisional oscillator and a set of flip-flops. The optimal number of flip-flops can be determined through an area optimization process. The proposed power-on reset circuit thresholds demonstrate the process, voltage, temperature (PVT) tolerance, facilitated by the use of resistors of the same type. Notably, the thresholds and provided delay for this circuit are supply-rise-time independent. The structure has been implemented in a 0.18-μm CMOS technology, occupying an active area of 48 × 40 μm².