International Journal of Circuit Theory and Applications最新文献

{"title":"A Novel Asymmetric Cascaded H-Bridge Concept Using Switched Rectifier","authors":"Hasan Hataş","doi":"10.1002/cta.70023","DOIUrl":"https://doi.org/10.1002/cta.70023","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, a new concept is proposed for classical cascaded H-bridge (CHB) multilevel inverter (MLI) configurations. The proposed structure includes a DC-DC converter circuit (switching rectifier) that generates multiple asymmetric voltages at the input of the H-bridges. This SR circuit can generate different voltages (1<i>V</i>_DC and 2<i>V</i>_DC) at the same terminals, thus providing a compact solution to existing topologies. Multiple DC bus voltages are generated using HFL and SR, resulting in higher levels at the output compared to traditional asymmetric source configurations. Three H-bridge circuits that generate a 27-level in trinary configuration and a 15-level in binary configuration are combined with two SRs to produce a 35-level output. With an output efficiency of over 96%, the topology offers low power losses and sustainable performance, making it an energy-efficient and cost-effective alternative. The high output level and stable performance characteristics make this hybrid CHB structure suitable for renewable energy systems, electric vehicles, and general power electronics applications. A comprehensive comparison with other MLI designs in the literature is made, and the simulation results are validated with a low-power prototype.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 8","pages":"4754-4768"},"PeriodicalIF":1.6,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144768072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-Way and Poly-Phase Differential Phase Shifters With Highly Reduced Footprint","authors":"Chuan Shao,&nbsp;Rong Cai,&nbsp;Xinnai Zhang,&nbsp;Kai Xu","doi":"10.1002/cta.70030","DOIUrl":"https://doi.org/10.1002/cta.70030","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper introduces the conception, synthesis, and fabrication of a set of miniaturized five-way differential phase shifters that incorporate an integrated filtering capability. In order to achieve a highly reduced footprint in this design, the three-line coupled structure (TLCS) is applied as the phase-shifting element in each phase-shifting branch. The working principles of the TLCS have been subjected to in-depth scholarly investigation. Benefitting from the miniaturized size of the TLCS, the electric size of the phase-shifting element is about 0.005 <i>λ</i>_g², which exhibits a considerably smaller scale when juxtaposed with state-of-the-art solutions. To confirm the feasibility of the concept and synthesis strategy, a group of five-way poly-phase phase shifters has undergone design, fabrication, and measurement, and design guidelines are summarized accordingly. The measured results demonstrate that the achieved relative phase-shift values are 45° ± 1.7°, 90° ± 2.3°, 135° ± 3.2°, and 180° ± 4.1° across a 53% fractional bandwidth, accompanied by amplitude imbalances that do not exceed 0.15 dB across the various phase-shifting pathways.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 8","pages":"4985-4993"},"PeriodicalIF":1.6,"publicationDate":"2025-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144768064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Constant Current and Constant Voltage Dual-Output Wireless Power Transfer System Based on Receiving Side Decoupling: Analysis, Design, and Verification","authors":"Le Yu,&nbsp;Shujia Xu,&nbsp;Xuebin Zhou,&nbsp;Lin Yang,&nbsp;Ran Li,&nbsp;Xiaoyu Zhang","doi":"10.1002/cta.4528","DOIUrl":"https://doi.org/10.1002/cta.4528","url":null,"abstract":"<div>\u0000 \u0000 <p>In order to solve the problem that the automatic guided vehicle requires load-independent constant current (CC) and constant voltage (CV) dual-type outputs, it is necessary to design a dual-output wireless power transfer (WPT) system with different output types. However, the existing dual-output WPT systems have problems such as unnecessary cross-coupling, limited space utilization, and complex control methods; therefore, this paper proposes a CC and CV dual-output WPT system based on receiving side decoupling. In the system, the transmitting side coil uses a Q-type coil and a solenoid coil that are connected in series and wound vertically, and the receiving side coil uses a Q-type coil and a solenoid coil that are independent and perpendicular to each other; the mutually perpendicular Q-coil and solenoid coils are naturally decoupled, thus eliminating the effects of cross coupling in the system. First, the decoupling characteristics of the proposed magnetic coupler are analyzed in detail. Second, a mathematical model is established based on the decoupling of the magnetic coupler, and the load-independent output characteristics of the dual-output WPT system and the input impedance showing pure resistance characteristics are derived in detail. Then, the output characteristics under ZPA conditions that can be achieved by the system are further verified through simulation analysis. In addition, in order to reduce the conduction loss of the switch tube in the system, the influence of the change of compensation component parameters on the realization of zero voltage switching is analyzed through normalized simulation. Finally, an experimental prototype is built, achieving CC output of 3.5 A and CV output of 70 V, verifying the correctness of the above theoretical analysis. In addition, when the first receiving side load \u0000<span></span><math>\u0000 <msub>\u0000 <mrow>\u0000 <mi>R</mi>\u0000 </mrow>\u0000 <mrow>\u0000 <mi>B</mi>\u0000 <mn>1</mn>\u0000 </mrow>\u0000 </msub></math> is 30 \u0000<span></span><math>\u0000 <mi>Ω</mi></math> and the second receiving side load \u0000<span></span><math>\u0000 <msub>\u0000 <mrow>\u0000 <mi>R</mi>\u0000 </mrow>\u0000 <mrow>\u0000 <mi>B</mi>\u0000 <mn>2</mn>\u0000 </mrow>\u0000 </msub></math> is 19 \u0000<span></span><math>\u0000 <mi>Ω</mi></math>, the peak efficiency can reach 92.6%.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 9","pages":"5579-5591"},"PeriodicalIF":1.6,"publicationDate":"2025-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145012358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Cost Open-Loop Digital Spread Spectrum Clock Divider for Class-D Audio Amplifier in 180-nm CMOS","authors":"Yufei Wu,&nbsp;Zhaoquan Zeng","doi":"10.1002/cta.4537","DOIUrl":"https://doi.org/10.1002/cta.4537","url":null,"abstract":"<div>\u0000 \u0000 <p>This brief report introduces a low-cost, open-loop digital spread spectrum clock divider (DSSCD) specifically designed for class-D audio amplifier applications. Unlike conventional spread spectrum clock generators that rely on feedback architectures, such as phase-locked loops (PLLs) and delay-locked loops (DLLs), the proposed DSSCD employs a feed-forward architecture using simple, fully synthesizable circuit blocks combined with an analog harmonic suppresser. The core design features a counter-based clock divider (CBCD) with dynamically adjustable division factors. This clock divider is driven by a \u0000<span></span><math>\u0000 <mi>Δ</mi>\u0000 <mi>Σ</mi></math>-modulated triangular waveform, which continuously varies the division ratio, effectively spreading the clock spectrum and reducing spectral peaks that contribute to electromagnetic interference (EMI). A digital waveform generator produces the triangular input signal for modulation, while the harmonic suppresser attenuates high-frequency harmonics to smooth the divider's output. Fabricated in 180-nm digital process and operating at a 1.2-V supply, the proposed DSSCD achieves an output frequency range from 96 kHz (12 fs, 1 fs = 8 kHz) to 1.024 MHz (128 fs), with a frequency spread range from 0% to 10%. The design occupies an area of 0.0108 mm\u0000<span></span><math>\u0000 <msup>\u0000 <mrow></mrow>\u0000 <mrow>\u0000 <mn>2</mn>\u0000 </mrow>\u0000 </msup></math> and consumes 252 \u0000<span></span><math>\u0000 <mi>μ</mi></math>W with 147.456-MHz (18,432-fs) input and 192-kHz (24-fs) output. By simplifying circuit complexity while reducing power consumption and chip area, the proposed DSSCD provides an efficient and cost-effective spread spectrum solution for class-D audio applications.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 7","pages":"4000-4007"},"PeriodicalIF":1.8,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144525017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Distributed Secondary Control for Islanded DC Microgrids With Event-Triggered Quantization Communication","authors":"Baoyan Wang,&nbsp;Xin Cai,&nbsp;Xinyuan Nan","doi":"10.1002/cta.4450","DOIUrl":"https://doi.org/10.1002/cta.4450","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, islanded multibus DC microgrids (MGs) with constrained digital communication network are considered. A novel distributed control strategy based on an event-triggered quantization communication scheme is proposed in the secondary layer for regulating global average voltage and load currents sharing. In particular, each distributed generator (DG) sends quantized information to its neighboring DGs only when the triggered condition is satisfied; thus, the communication burden in terms of communication frequency and the amount of data transmitted through the network is significantly reduced. The introduction of both event-triggered and quantized schemes raises the difficulty in stability analysis of the designed control. A comprehensive analysis via LaSalle's invariant-set principle is provided to give sufficient conditions for voltage regulation and precise current sharing. Finally, the proposed control strategy is further validated by an example simulation.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 7","pages":"4359-4372"},"PeriodicalIF":1.8,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Single Excitation Source Multistage Wireless Power Transfer System for Enabling Flexible Joint Rotation of ROV Manipulator","authors":"Longyang Wang,&nbsp;Jiangui Li,&nbsp;Xiaokang Yin,&nbsp;Baoping Cai,&nbsp;Longlong Zhang,&nbsp;Chen Chen","doi":"10.1002/cta.4510","DOIUrl":"https://doi.org/10.1002/cta.4510","url":null,"abstract":"<div>\u0000 \u0000 <p>This article presents a novel single excitation source multistage wireless power transfer (WPT) system, capable of efficiently delivering power to multiple loads via multistage magnetic resonance coupling. This system facilitates concurrent wireless energy transmission at different locations, eliminates cable limitations on manipulator flexibility, prevents cable damage due to frequent twisting, and exhibits great potential in applications like manipulator arms for remotely operated vehicles (ROVs). Firstly, principle of the multistage WPT system based on LCC compensation and its power supply mode in multiple joints of a manipulator arm were introduced. Secondly, the formulations for calculating the input, output, and losses of a multistage WPT system were derived. Thirdly, taking the two-stage WPT system as an example, parameter optimization design was conducted, and the influence of key parameters on the system's output characteristics was studied. Finally, an experimental prototype with two-stage system was constructed. The prototype achieved transfer efficiency of 83.3%, with outputs of 100.26 and 94.85 W for stages one and two, respectively. This article presents a single excitation source multistage wireless power transfer (WPT) system, capable of efficiently delivering power to multiple loads via multistage magnetic resonance coupling. This system facilitates concurrent wireless energy transmission at different locations, eliminates cable limitations on manipulator flexibility, and exhibits great potential in applications like manipulators.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5789-5801"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual-Band Input–Output Waveform Engineered High-Efficiency Power Amplifier With Large Frequency Ratio and Adjustable Transmission Zeros","authors":"Zhenghua Wei,&nbsp;Qiang Liu,&nbsp;Guangxing Du,&nbsp;Wang Liu,&nbsp;Guolin Li","doi":"10.1002/cta.4513","DOIUrl":"https://doi.org/10.1002/cta.4513","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper proposes two novel modes based on input–output waveform engineering and a compact dual-band output matching network (DB OMN) with two adjustable transmission zeros (TZs), for the design of dual-band power amplifiers (DBPAs) with large frequency ratio. For the first time, the two modes considering input nonlinearity of the transistor are leveraged to construct two new expanded optimum drain load impedance spaces (DLISs), thereby reducing the complexity of designing DB OMNs. Based on this, the maximum frequency ratio of the proposed DB OMN can theoretically reach 7.6. Additionally, two adjustable TZs can be produced, and its frequency ratio is confirmed in the range from 1.6 to 7.6. For demonstration, a prototype operating at 0.7 and 2.64 GHz is implemented with frequency ratio of 3.8, and two TZs at 0.9 and 2.08 GHz are purposefully introduced. Measured results show that the DBPA exhibits the power added efficiencies (PAEs) of 83.2% and 70.9% with output powers of 41.9 and 40.9 dBm at 0.7 and 2.64 GHz, respectively. Meanwhile, the output powers of only 1.9 and −8.1 dBm are obtained at 0.9 and 2.08 GHz, respectively.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5626-5637"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Parallel Hardware Architecture for GF(p) Elliptic Curve Point Multiplication on FPGA","authors":"Ruoyu Wu,&nbsp;Binchao Yu,&nbsp;Zhaofeng Chen,&nbsp;Xiangyu Li,&nbsp;Guanzhong Tian","doi":"10.1002/cta.4495","DOIUrl":"https://doi.org/10.1002/cta.4495","url":null,"abstract":"<div>\u0000 \u0000 <p>Elliptic curve point multiplication is a critical component in elliptic curve cryptography, serving as a key computational module for fast and secure encryption. To enhance computational performance, parallelism and pipelining are commonly employed techniques in hardware design. However, the stringent computational dependencies in elliptic curve cryptography and the complex combinational logic required for large integer multiplication present significant challenges for area-efficient hardware design, leading to performance bottlenecks. This paper aims to improve system frequency by employing multilevel pipeline partitioning to optimize the critical path. We implement an efficient, low-latency, high-radix modular multiplication unit by combining parallel multiplication with deep pipelining. Building on this high-frequency, high-throughput modular multiplication unit, we propose a high-performance ECPM architecture. Multistage pipelines are inserted into each unit of the ECPM to maintain high-frequency operation across the entire system. Additionally, by analyzing and refining the combined point quadruple-point addition computation flow and data dependencies, we introduce a no-idle parallel modular multiplier architecture, which improves cycle efficiency per computation iteration by 9<i>%</i>. Experimental results on the Virtex-7 FPGA platform demonstrate that, compared with related works, the proposed ECPM architecture achieves a 30<i>%</i> improvement in Area \u0000<span></span><math>\u0000 <mo>×</mo></math> Time.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5839-5850"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145227966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An SDPF RISC-V Processor With 55.9% Dhrystone Improvement Using Two-Stage Pseudo-Pipelined Architecture for IoT Applications","authors":"Wenji Mo,&nbsp;Jingjing Liu,&nbsp;Yuchen Wang,&nbsp;Feng Yan,&nbsp;Bingjun Xiong,&nbsp;Jian Guan","doi":"10.1002/cta.4514","DOIUrl":"https://doi.org/10.1002/cta.4514","url":null,"abstract":"<div>\u0000 \u0000 <p>Embedded Internet of Things (IoT) nodes are required to perform lightweight tasks such as information monitoring and simple signal processing. A crucial component of low-power embedded IoT sensors is the low-power processor. Due to the constraints of operating conditions, there are stringent requirements on the power consumption and area of the processor. To minimize the power and area, this paper proposes a low-power RV32I processor based on the RISC-V instruction set architecture (ISA), which adheres to a serial data path. To enhance the energy efficiency of the serial data path followed (SDPF) processor, this paper proposes a pseudo-pipeline architecture. By partitioning and combining certain instruction lifecycle tasks, a two-stage pseudo-pipeline structure is implemented, thereby reducing the cycles per instruction (CPI) of the SDPF processor. The proposed processor is designed using Verilog HDL, and FPGA prototype validation demonstrates that the proposed processor achieves at least 18% fewer resource compared with the traditional parallel 32-bit RISC-V processors and 55.9% performance improvement compared with the previous SDPF processors. The proposed processor is implemented using a standard 0.18-μm CMOS process. The post-layout simulation results indicate that it has at least 9.6% less area and 37.5% lower dynamic power consumption compared with traditional parallel 32-bit processor. Additionally, it achieves a 40.9% increase in the performance to power ratio compared with the previous SDPF RV32I processor.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5827-5838"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145227965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CMOS Design of a Chaos-Based Masking System for Biomedical Signals Applications","authors":"Eduardo Juárez-Mendoza,&nbsp;Gregorio Zamora-Mejia,&nbsp;Esteban Tlelo-Cuautle,&nbsp;Alejandro Díaz-Sánchez","doi":"10.1002/cta.4500","DOIUrl":"https://doi.org/10.1002/cta.4500","url":null,"abstract":"<div>\u0000 \u0000 <p>This work shows the development of an electrocardiogram (ECG) data masking system based on double-scroll synchronized chaotic oscillators. The contribution is devoted to the introduction of a CMOS implementation of a double-scroll chaotic oscillator, which is designed by taking advantage of the intrinsic hyperbolic tangent-type characteristic of the operational transconductance amplifier (OTA). The chaotic behavior of the CMOS oscillator is guaranteed by plotting the bifurcation diagram and evaluating the Lyapunov exponents. In this manner, a masking system based on CMOS chaotic systems is designed to protect privacy while transmitting ECG signals effectively. Basically, the chaotic time series is processed to generate pseudorandom signals in a continuous-time domain. Mathematical modeling and simulation results under a UMC 180-nm CMOS fabrication process demonstrate that the proposed masking system is well suited to provide hardware-level security in the chaotic encryption of biomedical signals.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5802-5815"},"PeriodicalIF":1.6,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}