International Journal of Circuit Theory and Applications最新文献

{"title":"A Single-Switch Misalignment-Tolerant LCC-LCC Compensated WPT System With Inherent Constant Current and Constant Voltage Outputs","authors":"Sheng Ren,&nbsp;Xiaoqing Wang,&nbsp;Tiesheng Yan,&nbsp;Yifan Wang,&nbsp;Jianping Xu,&nbsp;Ping Yang","doi":"10.1002/cta.70307","DOIUrl":"https://doi.org/10.1002/cta.70307","url":null,"abstract":"<div>\u0000 \u0000 <p>Wireless power transfer (WPT) charger with constant current (CC) output and constant voltage (CV) output has gained significant attention in battery charging applications. The coil misalignment and wide load resistance range present challenges to the design and control of WPT charger. A single-switch LCC-LCC compensated WPT system with inherent CC output and CV output is proposed in this paper. In the proposed WPT system, only one switch is used, which reduces the number of switches and the corresponding driver circuits. The shoot-through risk in the half/full-bridge inverter can be avoided. The asymmetric coil structure is adopted to smooth the variations of the coupling coefficient of the loosely coupled transformer (LCT), which improves the system's misalignment tolerance. In addition, the transition from CC output to CV output is automatically completed according to the load conditions, which eliminates battery state detection and control strategy. The proposed WPT system has advantages of low cost, low complexity, high reliability, and wide zero voltage switching (ZVS) and misalignment tolerance range. A laboratory prototype with 3-A output current in CC mode and 72-V output voltage in CV mode is constructed to verify the analysis. The experimental results show that the system can achieve the required inherent CC and CV outputs when the misalignment distance in the horizontal direction is within 70 mm, and the peak efficiency of 90.9% is realized.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4813-4829"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Symmetric Fractional-Order LADRC-PLL With Impedance Reshaping for Grid-Connected Inverter in Weak Grid","authors":"Yibo Li,&nbsp;Wei Cai,&nbsp;Qingbo Guo,&nbsp;Jiuliang Sun,&nbsp;Lei Yang","doi":"10.1002/cta.70302","DOIUrl":"https://doi.org/10.1002/cta.70302","url":null,"abstract":"<div>\u0000 \u0000 <p>In weak grid conditions, the interaction between the phase-locked loop (PLL) and the grid impedance can introduce negative damping, potentially exciting low-frequency oscillations that impair the stability of a grid-connected inverter (GCI). Although the linear active disturbance rejection control (LADRC) approach can strengthen PLL robustness, it still exhibits limitations in suppressing the frequency coupling effect (FCE) and in improving dynamic response. To overcome these issues, a symmetric fractional-order LADRC-PLL is proposed, which incorporates an impedance reshaping strategy to further improve the stability of the GCI. First, the influence of the fractional-order operators on the dynamic characteristics of the PLL and the output impedance of the GCI is analyzed through frequency-domain modeling, revealing the intrinsic mechanism responsible for the introduction of negative damping. Then, a composite phase compensation filter is designed to enhance the phase margin of the output impedance, whereas a real-time frequency estimation–based phase angle correction method is employed to mitigate voltage–current phase errors caused by frequency deviations. The effectiveness of the proposed approach in mitigating FCE, enhancing dynamic performance of the PLL, and reinforcing stability under weak grid conditions is confirmed through simulation and hardware-in-the-loop (HIL) experiments.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4830-4845"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Phase Noise-Aware Adaptive Master–Slave Charge-Pump Fast Locking Phase-Locked Loops","authors":"Fei Xiang,&nbsp;Pengshuai Dong,&nbsp;Xiangjun Wang,&nbsp;Shuolei Cao,&nbsp;Jinchan Wang,&nbsp;Bo Liu","doi":"10.1002/cta.70306","DOIUrl":"https://doi.org/10.1002/cta.70306","url":null,"abstract":"<div>\u0000 \u0000 <p>A fast-locking, low-jitter, and low-power phase-locked loop (PLL) adopting adaptive master–slave charge-pump architecture for L-band RF wireless communication is proposed. By designing a novel adaptive switched logic control (ASLC) circuit combined with an auxiliary charge-pump set, the proposed PLL can effectively achieve adaptive acceleration compensation in phase locking benefited from the multipath charging effect while controlling the increase of unexpected phase noise and power dissipation. Transfer function estimation on MATLAB is performed for phase noise modeling to predict the output noise and RMS jitter in CPPLL. Based on SMIC 180 nm/1.8 V standard CMOS technology, Cadence-based circuit design and performance simulation are performed. The results demonstrate that the locking time from startup to stable 1.137GHz frequency output is only 0.23 μs, the RMS jitter is as low as 266 fs with just 5.699 mW power consumption, and the overall FoM value can be as high as 243.9 dB. The proposed <i>L</i>-band doubled CPPLL can be effectively applied in RF wireless communication signal generation and frequency synthesis such as satellite down-frequency receiving, optical signal modulation, and digital audio broadcast (T-DAB).</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"5062-5070"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Primary Ended Switched Inductor–Switched Capacitor Based High-Gain DC–DC Converter","authors":"P. Raviteja,&nbsp;B. L. Narasimharaju","doi":"10.1002/cta.70312","DOIUrl":"https://doi.org/10.1002/cta.70312","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper introduces the Primary Ended Switched Inductor–Switched Capacitor High-Gain (PESL-SCHG) converter, designed to achieve high voltage gain while operating at a reduced duty cycle. This operating characteristic significantly reduces conduction losses in the converter circuit. The PESL-SCHG converter incorporates both switched inductor and switched capacitor components, ensuring a continuous input current that enhances the overall system efficiency. A detailed analysis of the converter, including its operational principles, steady-state behavior, and stress analysis of both voltage and current, is presented. The performance of the proposed PESL-SCHG converter is compared with that of existing converters to highlight its advantages and improvements. To validate the claims made about the converter's performance, a 20–400 V, 200-W hardware prototype is tested. The experimental results confirm the converter's enhanced capabilities and efficiency, demonstrating the PESL-SCHG converter's suitability for high-gain applications.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4993-5008"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Speed Control of Electric Propulsion Systems With Enhanced Suppression of Periodic and Aperiodic Disturbances","authors":"Dongliang Liu,&nbsp;Haidong Chen,&nbsp;Weijie Lin,&nbsp;Haobo Ma,&nbsp;Wenhao Fan,&nbsp;Lijun Chen,&nbsp;Feng Qu","doi":"10.1002/cta.70315","DOIUrl":"https://doi.org/10.1002/cta.70315","url":null,"abstract":"<div>\u0000 \u0000 <p>To enhance the suppression performance of a permanent magnet synchronous motor (PMSM) in an electric propulsion system against both periodic and aperiodic disturbances, this paper proposes a quasi-resonant-controller-based cascaded linear active disturbance rejection control strategy (QRC-CLADRC) applied to the speed loop. The method adopts a cascaded linear extended state observer (CLESO) structure, in which the front-stage linear extended state observer (LESO) first processes the dominant disturbances, providing the subsequent stage with an initially “purified” state estimation. The back-stage LESO further eliminates the residual disturbances based on the compensation from the front stage. Moreover, a quasi-resonant controller (QRC) is embedded into the back-stage LESO to improve suppression of periodic speed fluctuations. A linear state error feedback control (LSEFC) mechanism is then designed to compensate for the estimated disturbances, thereby reducing speed ripple. The disturbance estimation performance, stability, and disturbance rejection capability of the system are theoretically analyzed. Finally, the effectiveness and superiority of the proposed method are validated on a 300-W electric propulsion experimental bench.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4846-4858"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simplified Small-Signal Modeling Method for Non-Isolated High Step-Up Converters","authors":"Samuel Antonio Macedo de Oliveira,&nbsp;Pedro Herysson Almeida da Silva,&nbsp;Fernando Lessa Tofoli,&nbsp;Dalton de Araújo Honório","doi":"10.1002/cta.70606","DOIUrl":"https://doi.org/10.1002/cta.70606","url":null,"abstract":"<p>This work presents a generalized small-signal modeling methodology for a family of DC–DC converters based on the four-state switching cell with a wide conversion range (WCR-4SSC) operating in continuous conduction mode (CCM). Although the proposed approach is derived from the well-established state-space averaging (SSA) technique, it simplifies the modeling process by representing the six operating stages as an equivalent two-stage solution. The resulting averaged model is defined in terms of an equivalent duty cycle, whose expression depends on the converter operating region (<i>R</i>₁, <i>R</i>₂, or <i>R</i>₃), which is determined by the rated duty cycle. A step-by-step procedure for obtaining the averaged model and its subsequent linearization is presented and applied to a DC–DC Ćuk converter based on the WCR-4SSC, yielding several transfer functions of interest. To validate the proposed methodology, the analytical model is compared with the switched converter. The results show good agreement in both the frequency and time domains, confirming the accuracy of the proposed solution.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4859-4875"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/cta.70606","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Improved Single-Switch Quadratic Boost Converter With Lower Voltage Stress and Ultrahigh Voltage Gain With Switched Capacitor–Inductor Network for Solar Photovoltaic Systems","authors":"Ravi Kumar Kanaparthi,&nbsp;Jay Prakash Singh,&nbsp;Makarand Sudhakar Ballal","doi":"10.1002/cta.70318","DOIUrl":"https://doi.org/10.1002/cta.70318","url":null,"abstract":"<div>\u0000 \u0000 <p>This article proposes an improved single-switch quadratic boost converter (AISSQBC) for solar photovoltaic applications, offering an ultrahigh voltage gain with reduced voltage stress. The proposed converter is derived from the conventional quadratic boost converter (QBC), which is also a biquadratic boost converter (BQBC). It incorporates an additional capacitor and two diodes, achieving an ultrahigh voltage gain at the lower duty ratio (nearly 24 at the duty cycle of 50%) using a switched capacitor–inductor network. The proposed converter is able to produce six times higher voltage gain than QBC and 1.5 times higher voltage gain than BQBC. The proposed converter has 3.0% improvement in efficiency at a full load of 200 W, with the same input voltage of 24 V as compared with the conventional QBC. A single switch with a series-connected capacitor reduces the normalized voltage stress on the switch, enabling the use of lower rated, cost-effective switches. Presented comprehensive steady-state analysis under CCM, DCM, and BCM conditions, as well as small-signal AC modeling, power loss calculation, and cost evaluation for a 200-W power capacity. The voltage gain is derived for both ideal and nonideal conditions. The dynamic response under voltage-control mode is validated using a proportional-integral controller with step load variations. The maximum efficiency of the proposed converter is reported 96% for 180 W and 93.02% for 200 W of full load. A 200-W, 50-kHz prototype is developed and experimentally tested in the laboratory.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4971-4992"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Subthreshold Time-Mode All-Digital DLL With Built-In Linearization","authors":"Fei Yuan,&nbsp;Wenhao Wu,&nbsp;Yushi Zhou","doi":"10.1002/cta.70549","DOIUrl":"https://doi.org/10.1002/cta.70549","url":null,"abstract":"<p>Subthreshold charge pump delay-locked loops (DLLs), often favored over their all-digital counterparts for their small silicon footprint and low power consumption, suffer from the fundamental drawback of inability to lock to low-frequency (kHz) timing references due to the leakage-induced phase errors in the idle state of the charge pump and the exceedingly long duration of the idle state. To combat this drawback, this paper presents a subthreshold time-mode all-digital DLL for low-frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. The phase error of the DLL is processed by a time-mode proportional block (pBlock) implemented using a delay line time-to-digital converter (TDC) for rapid phase error correction and an integral block (iBlock) implemented using a bidirectional gated delay line time integrator for static phase error elimination. The delay line is powered by a subthreshold voltage generator whose output is controlled by the pBlock and iBlock. The transfer characteristics of the voltage generator are profiled as per the opposite of the delay line, such that a linear relation between the tuning bit of the supply voltage and the delay of the delay line is obtained, thereby reinstating the intrinsic stability of the DLL with a drastically improved area/power efficiency. The proposed DLL is designed in a TSMC 130-nm 1.2-V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using <i>Spectre</i> with BSIM3v3 device models. Simulation results show the DLL locks to a 100-kHz 0–0.6-V timing reference at FF/0.6 V/\u0000<span></span><math>\u0000 <mo>−</mo></math>20°C, TT/0.6 V/27°C, and SS/0.6 V/60°C with no accumulated static phase error. The DLL occupies 0.00985 mm\u0000<span></span><math>\u0000 <msup>\u0000 <mrow></mrow>\u0000 <mrow>\u0000 <mn>2</mn>\u0000 </mrow>\u0000 </msup></math>, offers a 59–200-kHz lock range, 1.3% mean-square-root jitter, and consumes 198 nW.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"5045-5061"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/cta.70549","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Current Conveyor Implementation of Double Differential Amplifier for Active Electrodes","authors":"Carla Caruso,&nbsp;Alfio Dario Grasso,&nbsp;Federico N. Guerrero,&nbsp;Gaetano Palumbo","doi":"10.1002/cta.70611","DOIUrl":"https://doi.org/10.1002/cta.70611","url":null,"abstract":"<p>This work presents two transistor-level solutions to implement a double differential (DD) amplifier by using a current conveyor, which can be used as front-ends in standalone active electrodes for superficial electromyography (sEMG) applications. Currently published DD amplifiers highlight the advantages of using second-generation current conveyors to achieve simplified topologies, but they do not provide transistor level implementations. In this work, two solutions are presented and analyzed in detail.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"5019-5029"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/cta.70611","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault Diagnosis and Fault-Tolerant Control Strategies for Highly Reliable Electric Drive System Based on Dual-Winding Fault-Tolerant Permanent Magnet Motor","authors":"Jie Li,&nbsp;Tingyuan Zhang,&nbsp;Xuefeng Jiang,&nbsp;Wangyang Zhou,&nbsp;Jichen Niu","doi":"10.1002/cta.70291","DOIUrl":"https://doi.org/10.1002/cta.70291","url":null,"abstract":"<div>\u0000 \u0000 <p>To achieve high performance, the electric drive system in aerospace equipment is becoming increasingly critical. This paper proposes a highly reliable electric drive system based on the dual-winding fault-tolerant permanent magnet motor (DFPMM). The proposed drive system offers the advantage of requiring fewer additional components and achieving high utilization after fault occurs. For this proposed drive system, a robust fault diagnosis and fault-tolerant control strategy are presented. The proposed fault diagnosis strategy, based on processing acquired current signals, enables rapid and accurate diagnosis and localization of open-circuit (OC) faults in windings or power switches within the system. Crucially, it exhibits strong robustness, preventing misdiagnosis under conditions such as no-load, light-load, or torque/speed transients. The proposed fault-tolerant control strategy is based on the principle of constant magnetic flux. By removing the faulty phase and activating the neutral point switch, the current of the remaining phases is reconstructed, thereby enabling the DFPMM to operate fault-tolerantly. Simulation and experimental outcomes confirm the accuracy and efficacy of the proposed fault diagnosis and fault-tolerant control methods.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 10","pages":"4891-4906"},"PeriodicalIF":1.4,"publicationDate":"2026-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149100373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}