A Low-Cost Open-Loop Digital Spread Spectrum Clock Divider for Class-D Audio Amplifier in 180-nm CMOS

Abstract

This brief report introduces a low-cost, open-loop digital spread spectrum clock divider (DSSCD) specifically designed for class-D audio amplifier applications. Unlike conventional spread spectrum clock generators that rely on feedback architectures, such as phase-locked loops (PLLs) and delay-locked loops (DLLs), the proposed DSSCD employs a feed-forward architecture using simple, fully synthesizable circuit blocks combined with an analog harmonic suppresser. The core design features a counter-based clock divider (CBCD) with dynamically adjustable division factors. This clock divider is driven by a $\Delta \Sigma$-modulated triangular waveform, which continuously varies the division ratio, effectively spreading the clock spectrum and reducing spectral peaks that contribute to electromagnetic interference (EMI). A digital waveform generator produces the triangular input signal for modulation, while the harmonic suppresser attenuates high-frequency harmonics to smooth the divider's output. Fabricated in 180-nm digital process and operating at a 1.2-V supply, the proposed DSSCD achieves an output frequency range from 96 kHz (12 fs, 1 fs = 8 kHz) to 1.024 MHz (128 fs), with a frequency spread range from 0% to 10%. The design occupies an area of 0.0108 mm ${}^2$ and consumes 252 $\mu$W with 147.456-MHz (18,432-fs) input and 192-kHz (24-fs) output. By simplifying circuit complexity while reducing power consumption and chip area, the proposed DSSCD provides an efficient and cost-effective spread spectrum solution for class-D audio applications.