International Journal of Circuit Theory and Applications最新文献

{"title":"An Ultrawideband Low-Voltage High-Gain Up-Conversion CMOS Mixer in CMOS 0.18-μm Technology for 3–16 GHz","authors":"Jun-Da Chen,&nbsp;Zhi-Xiang Chen","doi":"10.1002/cta.4505","DOIUrl":"https://doi.org/10.1002/cta.4505","url":null,"abstract":"<div>\u0000 \u0000 <p>This study presents a wideband up-converter mixer with a frequency range of 3 to 16 GHz. The mixer is based on TSMC's 0.18-μm CMOS technology. The architecture is based on a double-balanced mixer. The transconductance stage uses an enhanced common source architecture to amplify the intermediate frequency signal, thereby increasing the conversion gain. In addition, the body effect is exploited to reduce the turn-on voltage and DC power consumption of the transconductance stage. This design choice significantly reduces the power consumption of the mixer. The load inductor, a crucial component in the mixer's performance, uses a transformer-coupling technique. This technique involves coupling the inductor with a transformer to increase its inductance without significantly increasing its physical size. This allows for better performance in a smaller area. The measured conversion gain is 12 to 14.47 dB from 3 to 16 GHz with a flat of ±1.23 dB. The LO-to-RF port isolation varies between 21 and 36 dB. The input intercept point of the third order (IIP3) is between −7.5 and −4.8 dBm. Total DC power consumption is 4 mW when operating at 0.8 V. The total chip size for the up-conversion mixer is 1.09 × 1.2 mm².</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5595-5604"},"PeriodicalIF":1.6,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fast DC Analysis Method By Stochastic Matrix Iteration With Application to Multiport RC Network Reduction","authors":"Limin Hao,&nbsp;Guoyong Shi","doi":"10.1002/cta.4496","DOIUrl":"https://doi.org/10.1002/cta.4496","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, we present a novel formulation of the consensus principle for application to the DC analysis of a resistor–capacitor (RC) network driven by multiple sources. The consensus principle is essentially an iteration scheme that involves a row-stochastic matrix and converges. Implementation of this iteration method is deterministic, and its performance in solving the DC solutions of large RC networks excels the random walks (RWs) algorithm (which requires an implementation with random number generation). We report the performance comparison of applying this iteration algorithm and the RW algorithm in estimating the time constant of a multiport RC network which finds application in reducing large-scale multiport RC networks.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5781-5788"},"PeriodicalIF":1.6,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Planar Elliptical Coil Design With Helmholtz Structure Having a Uniform Magnetic Field for Nuclear Magnetic Resonance Spectroscopy","authors":"Mostafa Noohi,&nbsp;Hassan Faraji Baghtash,&nbsp;Habib Badri Ghavifekr,&nbsp;Ali Mirvakili","doi":"10.1002/cta.4491","DOIUrl":"https://doi.org/10.1002/cta.4491","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents the design and simulation of a novel planar elliptical coil for nuclear magnetic resonance (NMR) spectroscopy, fabricated as a printed circuit board (PCB) with an FR4 substrate. This technique offers valuable insights into molecular dynamics, structure, and interactions. A uniform magnetic field for spin excitation is generated by coupling two elliptical coils in a Helmholtz arrangement. The proposed coil stands out as an innovative alternative to traditional coils due to its improved efficiency, precise design, and reduced weight and spatial requirements. This work focuses primarily on the results obtained from finite element method (FEM) simulations. These simulations demonstrate a magnetic field uniformity of 92% across a broad frequency range (1–10 MHz), achieved through optimized tuning and matching capacitors. The maximum uniform magnetic flux density recorded within this frequency range is 220 μT. Furthermore, S11 and S21 parameters, along with the electric and magnetic field distributions, are calculated and analyzed to characterize RF signal interaction with the system. A detailed analysis of the S-parameters reveals optimal coil matching and tuning, minimizing energy losses. Ultimately, these results confirm the suitability of the proposed coil for portable NMR spectrometers, highlighting the simulation-driven design approach. This innovative design, with its significantly reduced weight, size, and manufacturing cost, promises considerable advancements in portable NMR spectroscopy.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5816-5826"},"PeriodicalIF":1.6,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 6.6-nA, 3.6-nW CMOS Current Reference With 0.4-V Supply Voltage","authors":"Azad Mahmoudi","doi":"10.1002/cta.4487","DOIUrl":"https://doi.org/10.1002/cta.4487","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents an all-MOSFET nanoampere (nA) current reference with a wide operating temperature range able to operate at a supply voltage as low as 0.4 V for ultra-low power applications. The temperature-compensated current is generated by combining two currents with opposite temperature coefficients (TCs), which are derived from two NMOS transistors biased with different complementary-to-absolute-temperature (CTAT) gate voltages. Self-biased self-cascode MOSFET (SBSCM) stages operating in the subthreshold region are utilized as the slope-adjustable linear CTAT voltage generators to achieve both low-power and low-voltage operation. Designed in a 130-nm CMOS process with an active area of 0.0021 mm², the proposed current reference achieves an average untrimmed TC of 308 ppm/°C over −40°C to 120°C while generating an output reference current of 6.6 nA. Post simulation results show that the power consumption is only 3.68 nW at the minimum supply voltage at room temperature.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5691-5700"},"PeriodicalIF":1.6,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Input Impedance IZO TFT Transimpedance Amplifiers With Current Buffer for Sensing and Transfer Applications","authors":"Mingjian Zhao,&nbsp;Laiqing Li,&nbsp;Hanyu Lu,&nbsp;Bin Li,&nbsp;Rongsheng Chen,&nbsp;Zhaohui Wu","doi":"10.1002/cta.4475","DOIUrl":"https://doi.org/10.1002/cta.4475","url":null,"abstract":"<div>\u0000 \u0000 <p>A structure for a low input impedance current buffer transimpedance amplifier (CBTIA) is presented, which holds great potential for flexible bioelectronic applications requiring high linearity sensing and transmission. Based on this structure, a tunable CBTIA and a low input impedance CBTIA circuits are implemented. The former utilizes a current sink input mode, where the voltage at the drain of common gate transistor is fed back to the gate of input current sink transistor in order to achieve low input impedance. A self-biasing optimization (SBO) technique is proposed for self-regulation of voltage headroom at each node. Additionally, the active load constructed by pseudo current source converts the current to voltage. Due to the current sink input mode, this design ensures that adjusting the transimpedance gain does not affect the input impedance. Furthermore, in the second circuit design, feedback is provided to the gate of an SBO regulated transistor in order to achieve even lower input impedance. The proposed CBTIAs were successfully implemented using 10-\u0000<span></span><math>\u0000 <mi>μ</mi></math> m IZO TFT technology. Test results show that the tunable CBTIA achieves a transimpedance gain range of 15.2 K to 47.4 K\u0000<span></span><math>\u0000 <mi>Ω</mi></math> while maintaining an unchanged 2 K\u0000<span></span><math>\u0000 <mi>Ω</mi></math> input impedance, and the low input impedance CBTIA achieves an input impedance less than 1.3 K\u0000<span></span><math>\u0000 <mi>Ω</mi></math> with a 61.7 K\u0000<span></span><math>\u0000 <mi>Ω</mi></math> transimpedance.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5669-5677"},"PeriodicalIF":1.6,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hybrid Class-B/C Mode-Switching VCO With 80% Current Efficiency and 202.2 dBc/Hz FoMT","authors":"Yue Yin,&nbsp;Haodong Lu,&nbsp;Haobo Qi,&nbsp;Ziting Feng,&nbsp;Xinbing Zhang,&nbsp;Chunming Lu,&nbsp;Xiaofei Qi","doi":"10.1002/cta.4494","DOIUrl":"https://doi.org/10.1002/cta.4494","url":null,"abstract":"<div>\u0000 \u0000 <p>In this article, an innovative class-B/C hybrid mode-switching technology is proposed, which can significantly improve the frequency tuning range (TR) and current efficiency of the voltage-controlled oscillator (VCO). Using the proposed technology, the class-B current in the traditional mode-switching VCO is replaced with the more efficient class-C current, thereby optimizing the power consumption and steady-state performance of the VCO. In addition, the use of a negative resistance structure with an opposite temperature coefficient improves the VCO's robustness to process, voltage, and temperature (PVT), especially to temperature changes. Thanks to the introduction of the low harmonic distortion of the class-C core and the source degeneration resistor, the flicker noise of the transistor and the phase noise (PN) of the VCO have been further improved. The VCO is designed and laid out in 65-nm complementary metal-oxide-semiconductor (CMOS) technology, with a total area of 0.12 \u0000<span></span><math>\u0000 <msup>\u0000 <mrow>\u0000 <mtext>mm</mtext>\u0000 </mrow>\u0000 <mrow>\u0000 <mn>2</mn>\u0000 </mrow>\u0000 </msup></math>.The postsimulation TR is 41.3% from 12.6 to 19.1 GHz. The PN and figure of merit turning (\u0000<span></span><math>\u0000 <msub>\u0000 <mrow>\u0000 <mtext>FoM</mtext>\u0000 </mrow>\u0000 <mrow>\u0000 <mi>T</mi>\u0000 </mrow>\u0000 </msub></math>) at 1-MHz offset are −113.2 and 202.2 dBc/Hz, respectively. The VCO consumes only 3.36 to 3.58 mA of current under a 1.2 V power supply, while maintaining an 80% current efficiency, which is significantly higher than the 63.7% of typical Class-B VCOs.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5769-5780"},"PeriodicalIF":1.6,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accurate and Fast Load Estimation Under Detuned Operation of IPT Systems","authors":"Hani Savaedi,&nbsp;Seyed Saeid Heidari Yazdi,&nbsp;Mehdi Bagheri,&nbsp;Alireza Namadmalan","doi":"10.1002/cta.4497","DOIUrl":"https://doi.org/10.1002/cta.4497","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper introduces an accurate and easy-to-implement algorithm for estimating the mutual inductance and load for inductive power transfer (IPT) systems. The algorithm employs a modified fundamental harmonic analysis (MFHA) and takes into account models of the battery and output filter. Using this algorithm, mutual inductance, output power, and the instantaneous voltage of the battery are predicted with less than 5% error. The formulations are presented for a series–series IPT system and generalized for non-symmetric conditions, meaning when the primary and secondary sides have different resonant frequencies. The proposed estimation method has been verified by different sensitivity analyses and simulations, using MATLAB and PSIM simulators. To validate the proposed algorithm, a laboratory prototype with operating frequencies of 82 to 85 kHz and maximum output power of 200 W was implemented and the accuracy of the estimations has been verified under different output power and operating frequencies for both symmetrical and non-symmetrical conditions.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5613-5625"},"PeriodicalIF":1.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145227979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Stronger Leakage Model Based on Conditional Generative Adversarial Networks for Correlation Power Analysis","authors":"Cheng Tang,&nbsp;Lang Li,&nbsp;Yu Ou","doi":"10.1002/cta.4486","DOIUrl":"https://doi.org/10.1002/cta.4486","url":null,"abstract":"<div>\u0000 \u0000 <p>Deep learning-based side-channel attacks (DL-SCA) have attracted widespread attention in recent years, and most of the researchers are devoted to finding the optimal DL-SCA method. At the same time, traditional SCA methods have lost their luster. However, traditional attacks still have certain advantages. Compared with the DL-SCA method, they do not require cumbersome engineering of tuning DL models and hyperparameters, making them easier to implement. Correlation power analysis (CPA), as a traditional SCA method, is still widely used in various analysis scenarios and plays an important role. In CPA, the leakage model is the key to simulating the power consumption, and it decides the attack efficiency. However, the existing leakage models are designed based on theory but ignore the actual attack scene. We found that conditional generative adversarial networks (CGAN) can ideally learn the target device's leakage characteristics and real power consumption. We let CGAN pre-learn the leakage of the target device, and then make the generator as the leakage model \u0000<span></span><math>\u0000 <mi>G</mi></math>. The \u0000<span></span><math>\u0000 <mi>G</mi></math> leakage model can characterize the leakages of the device and consider the presence of noise in the actual scenario. It can map the power consumption more realistically and accurately, which can lead to a more powerful CPA attack. In this work, three kinds of \u0000<span></span><math>\u0000 <mi>G</mi></math> leakage models (\u0000<span></span><math>\u0000 <mi>G</mi></math>1, \u0000<span></span><math>\u0000 <mi>G</mi></math>2, and \u0000<span></span><math>\u0000 <mi>G</mi></math>3 leakage models) corresponding to the labels least significant bit (LSB), hamming weight (HW), and identity (ID) of CGAN are discussed. The experimental results show that the \u0000<span></span><math>\u0000 <mi>G</mi></math>3 leakage model has better attack performance. Compared with the ordinary HW leakage model, the number of traces needed to recover the key on the ASCAD and SAKURA-AES datasets reduced by about 38.9% and 85.9%, respectively.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5851-5861"},"PeriodicalIF":1.6,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Broadband Dual-Band Negative Group Delay Circuit With Flat Group Delay","authors":"Yuwei Meng,&nbsp;Aixia Yuan,&nbsp;Zhenping Lan,&nbsp;Xianying Xu","doi":"10.1002/cta.4501","DOIUrl":"https://doi.org/10.1002/cta.4501","url":null,"abstract":"<div>\u0000 \u0000 <p>A broadband dual-band negative group delay circuit (NGDC) with flat group delay is proposed. Without the cascade structure, the proposed NGDC consists of an open-circuited coupled lines connected with a resistor through transmission lines and a matching network. The flatness of the negative group delay (NGD) and center frequencies of the lower and upper bands can be designed through changing the characteristic impedance of the transmission lines. And the NGD time is adjusted by modifying the parameters of the coupled line. Low GD ripple could be achieved by the proposed dual-band NGDC with a small circuit size. To verify the design concept, a dual-band NGDC is simulated, fabricated, and measured. The measured NGD times are −0.51 ns at the center frequencies of 0.32 and 1.39 GHz with insertion loss of 20.8 and 21.2 dB, respectively. The flat-NGD bandwidth reaches 32.8% from 0.275 to 0.380 GHz and 6.8% from 1.350 to 1.445 GHz with 10% group delay fluctuation.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5760-5768"},"PeriodicalIF":1.6,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Segmentation of IC Images in Integrated Circuit Reverse Engineering Using EfficientNet Encoder Based on U-Net++ Architecture","authors":"Hongnan Cheng,&nbsp;Chaozhi Yu,&nbsp;Chenguang Zhang","doi":"10.1002/cta.4485","DOIUrl":"https://doi.org/10.1002/cta.4485","url":null,"abstract":"<div>\u0000 \u0000 <p>Segmentation of electrical components and metal traces from integrated circuit (IC) images is crucial for IC reverse engineering. Existing image segmentation methods face significant challenges when applied to IC images, including high resolution, limited training data, and the need for precise segmentation. To address these issues, this study proposes a combined approach of segmentation and post-processing. During the segmentation stage, we use UNet++ as the base architecture, with EfficientNet-B7 as the encoder, resulting in an E-UNet++ model. This model effectively combines the efficiency and pre-training capabilities of EfficientNet with the ability of UNet++ to capture both global structural information and fine-grained boundary details in IC images, enabling it to effectively handle challenges such as high resolution and limited training samples. In the post-processing stage, to address potential noise caused by the insufficient utilization of spatial location information in network-based methods, we propose the use of Hough circle detection and median filtering to eliminate noise from vias and non-via regions. Compared to the suboptimal segmentation model, our proposed method achieved a 0.58% improvement in mean intersection over union (mIoU) and a 0.33% improvement in mean pixel accuracy (MPA) on the real-world dataset and a 0.78% improvement in mIoU and a 0.44% improvement in MPA on the open-source dataset. These experimental results demonstrate that our method effectively improves the accuracy of IC segmentation.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5913-5923"},"PeriodicalIF":1.6,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}