3-16 GHz超宽带低电压高增益上转换CMOS混频器,采用CMOS 0.18 μm工艺

IF 1.6 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Jun-Da Chen, Zhi-Xiang Chen
{"title":"3-16 GHz超宽带低电压高增益上转换CMOS混频器,采用CMOS 0.18 μm工艺","authors":"Jun-Da Chen,&nbsp;Zhi-Xiang Chen","doi":"10.1002/cta.4505","DOIUrl":null,"url":null,"abstract":"<div>\n \n <p>This study presents a wideband up-converter mixer with a frequency range of 3 to 16 GHz. The mixer is based on TSMC's 0.18-μm CMOS technology. The architecture is based on a double-balanced mixer. The transconductance stage uses an enhanced common source architecture to amplify the intermediate frequency signal, thereby increasing the conversion gain. In addition, the body effect is exploited to reduce the turn-on voltage and DC power consumption of the transconductance stage. This design choice significantly reduces the power consumption of the mixer. The load inductor, a crucial component in the mixer's performance, uses a transformer-coupling technique. This technique involves coupling the inductor with a transformer to increase its inductance without significantly increasing its physical size. This allows for better performance in a smaller area. The measured conversion gain is 12 to 14.47 dB from 3 to 16 GHz with a flat of ±1.23 dB. The LO-to-RF port isolation varies between 21 and 36 dB. The input intercept point of the third order (IIP3) is between −7.5 and −4.8 dBm. Total DC power consumption is 4 mW when operating at 0.8 V. The total chip size for the up-conversion mixer is 1.09 × 1.2 mm<sup>2</sup>.</p>\n </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5595-5604"},"PeriodicalIF":1.6000,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Ultrawideband Low-Voltage High-Gain Up-Conversion CMOS Mixer in CMOS 0.18-μm Technology for 3–16 GHz\",\"authors\":\"Jun-Da Chen,&nbsp;Zhi-Xiang Chen\",\"doi\":\"10.1002/cta.4505\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div>\\n \\n <p>This study presents a wideband up-converter mixer with a frequency range of 3 to 16 GHz. The mixer is based on TSMC's 0.18-μm CMOS technology. The architecture is based on a double-balanced mixer. The transconductance stage uses an enhanced common source architecture to amplify the intermediate frequency signal, thereby increasing the conversion gain. In addition, the body effect is exploited to reduce the turn-on voltage and DC power consumption of the transconductance stage. This design choice significantly reduces the power consumption of the mixer. The load inductor, a crucial component in the mixer's performance, uses a transformer-coupling technique. This technique involves coupling the inductor with a transformer to increase its inductance without significantly increasing its physical size. This allows for better performance in a smaller area. The measured conversion gain is 12 to 14.47 dB from 3 to 16 GHz with a flat of ±1.23 dB. The LO-to-RF port isolation varies between 21 and 36 dB. The input intercept point of the third order (IIP3) is between −7.5 and −4.8 dBm. Total DC power consumption is 4 mW when operating at 0.8 V. The total chip size for the up-conversion mixer is 1.09 × 1.2 mm<sup>2</sup>.</p>\\n </div>\",\"PeriodicalId\":13874,\"journal\":{\"name\":\"International Journal of Circuit Theory and Applications\",\"volume\":\"53 10\",\"pages\":\"5595-5604\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2025-03-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Circuit Theory and Applications\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1002/cta.4505\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Circuit Theory and Applications","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/cta.4505","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本研究提出了一种频率范围为3 ~ 16ghz的宽带上变频混频器。该混频器基于台积电的0.18 μm CMOS技术。该架构基于双平衡混合器。跨导级采用增强的共源架构来放大中频信号,从而增加转换增益。此外,利用体效应可以降低跨导级的导通电压和直流功耗。这种设计选择大大降低了混合器的功耗。负载电感是混合器性能的关键部件,采用变压器耦合技术。这种技术涉及到电感与变压器耦合,以增加其电感,而不显着增加其物理尺寸。这允许在更小的区域内获得更好的性能。测量到的转换增益在3 ~ 16 GHz范围内为12 ~ 14.47 dB,平坦度为±1.23 dB。低电平到射频端口的隔离度在21到36db之间变化。三阶(IIP3)输入截距点在−7.5 ~−4.8 dBm之间。工作电压为0.8 V时,总直流功耗为4mw。上转换混频器的总芯片尺寸为1.09 × 1.2 mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

An Ultrawideband Low-Voltage High-Gain Up-Conversion CMOS Mixer in CMOS 0.18-μm Technology for 3–16 GHz

An Ultrawideband Low-Voltage High-Gain Up-Conversion CMOS Mixer in CMOS 0.18-μm Technology for 3–16 GHz

This study presents a wideband up-converter mixer with a frequency range of 3 to 16 GHz. The mixer is based on TSMC's 0.18-μm CMOS technology. The architecture is based on a double-balanced mixer. The transconductance stage uses an enhanced common source architecture to amplify the intermediate frequency signal, thereby increasing the conversion gain. In addition, the body effect is exploited to reduce the turn-on voltage and DC power consumption of the transconductance stage. This design choice significantly reduces the power consumption of the mixer. The load inductor, a crucial component in the mixer's performance, uses a transformer-coupling technique. This technique involves coupling the inductor with a transformer to increase its inductance without significantly increasing its physical size. This allows for better performance in a smaller area. The measured conversion gain is 12 to 14.47 dB from 3 to 16 GHz with a flat of ±1.23 dB. The LO-to-RF port isolation varies between 21 and 36 dB. The input intercept point of the third order (IIP3) is between −7.5 and −4.8 dBm. Total DC power consumption is 4 mW when operating at 0.8 V. The total chip size for the up-conversion mixer is 1.09 × 1.2 mm2.

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来源期刊
International Journal of Circuit Theory and Applications
International Journal of Circuit Theory and Applications 工程技术-工程:电子与电气
CiteScore
3.60
自引率
34.80%
发文量
277
审稿时长
4.5 months
期刊介绍: The scope of the Journal comprises all aspects of the theory and design of analog and digital circuits together with the application of the ideas and techniques of circuit theory in other fields of science and engineering. Examples of the areas covered include: Fundamental Circuit Theory together with its mathematical and computational aspects; Circuit modeling of devices; Synthesis and design of filters and active circuits; Neural networks; Nonlinear and chaotic circuits; Signal processing and VLSI; Distributed, switched and digital circuits; Power electronics; Solid state devices. Contributions to CAD and simulation are welcome.
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