International Journal of Circuit Theory and Applications最新文献

{"title":"Integrated Wireless Transmitter for EV and AGV With High Interoperability","authors":"Chao Liu,&nbsp;Feijie Zheng,&nbsp;Yizhan Zhuang,&nbsp;Xiaoying Chen,&nbsp;Xiangpeng Cheng,&nbsp;Zhongqi Li,&nbsp;Yiming Zhang","doi":"10.1002/cta.4488","DOIUrl":"https://doi.org/10.1002/cta.4488","url":null,"abstract":"<div>\u0000 \u0000 <p>With the continuous expansion of wireless power transfer (WPT) in the field of electric vehicles (EVs) and automated guided vehicles (AGVs), there is a need for a wireless charger that can complete the charging of these two devices in a limited space. To fill the gap in this field, this paper proposes an integrated wireless transmitter (IWT) that is suitable for EV and AGV wireless charging under different frequencies, which can realize the radio energy transmission of two types of vehicles in one charging position. It can also tolerate different coupling structures in EV wireless charging, namely the unipolar (Q) and bipolar (DD) coils. The IWT is established by stacking the Q coil and the DD coil composed of two self-decoupled poles, combined with circuit configuration topologies. An experimental prototype is established to verify the interoperability performance. The proposed WPT system can achieve interoperability with EV wireless charging of Q or DD receiving coils at 85 kHz and AGV wireless charging at 200 kHz.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5605-5612"},"PeriodicalIF":1.6,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A mm-Wave Power VCO and Frequency Doubler Based on Class-C Architecture Using 130 nm CMOS Technology","authors":"Marwa Mansour,&nbsp;Islam Mansour","doi":"10.1002/cta.4480","DOIUrl":"https://doi.org/10.1002/cta.4480","url":null,"abstract":"<div>\u0000 \u0000 <p>This manuscript introduces a power voltage-controlled oscillator (PVCO) with a frequency doubler (FD), utilizing a complementary PMOS-NMOS architecture based on Class-C operation for millimeter-wave and fifth-generation (5G) systems. One output terminal of the VCO core is connected to a power stage operating at the fundamental frequency (\u0000<span></span><math>\u0000 <msub>\u0000 <mi>f</mi>\u0000 <mi>o</mi>\u0000 </msub></math>) in the 21.2–23.2 GHz frequency band. The other output terminal is linked to a FD and a power stage working at the second harmonic frequency (\u0000<span></span><math>\u0000 <mn>2</mn>\u0000 <msub>\u0000 <mi>f</mi>\u0000 <mi>o</mi>\u0000 </msub></math>), covering the 42–46.5 GHz frequency range. All inductors are designed on-chip using HFSS simulation tools, achieving a high-quality factor, large self-resonance frequency (SRF), and small die area. To enhance the frequency sensitivity of the PVCO and FD-PVCO, every band is split into three sub-bands by manipulating only one-pin switching voltage. The PVCO operates in the 21.24–23.2 GHz range, achieving a figure of merit (FoM) equal to −194.5 dBc/Hz, a phase noise (PN) equal to −108 dBc/Hz, and a maximum output power (\u0000<span></span><math>\u0000 <msub>\u0000 <mi>P</mi>\u0000 <mtext>out</mtext>\u0000 </msub></math>) equal to 5.74 dBm. Meanwhile, the FD-PVCO oscillates in the 42.48–46.4 GHz range, achieving a FoM of −200 dBc/Hz, a PN of −108 dBc/Hz, and an extreme \u0000<span></span><math>\u0000 <msub>\u0000 <mi>P</mi>\u0000 <mtext>out</mtext>\u0000 </msub>\u0000 <mo>=</mo>\u0000 <mn>2.9</mn>\u0000 <mspace></mspace>\u0000 <mi>dBm</mi></math>. The proposed design dissipates a DC-power equal to 2.4 mW and occupies an active area of 0.032 mm², whereas the overall chip size, including the pads, FD, and power stages, is 0.37 mm².</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5729-5738"},"PeriodicalIF":1.6,"publicationDate":"2025-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Hexagonal Switched Capacitor Unit (HSCU) Design With Seven-Level Multilevel Inverter Topology","authors":"Murat Karakılıç","doi":"10.1002/cta.4469","DOIUrl":"https://doi.org/10.1002/cta.4469","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, a new switched capacitor (SC) unit is proposed, which provides a solution for the multiple DC voltage requirement of multi-level inverters (MLIs). The proposed hexagonal switched capacitor unit (HSCU) contains SCs that have self-balancing ability and do not require any additional circuits. HSCU provides three voltage boosts using only one DC voltage source with four power switches, two capacitors, and two discrete diodes. A comparison with related topologies in the literature indicates that the proposed topology requires considerably fewer power devices than others. To suppress impulsive charging currents in the capacitors, a soft charging cell (SCC) is utilized. Experimental results demonstrate that the SCC effectively suppresses current peaks, contributing to improved circuit performance. In addition, the proposed 7L SC-MLI has successfully passed the simulation and experimental realization tests with nearest level control (NLC) modulation techniques and sinusoidal pulse width modulation (SPWM) modulation techniques. Response to dynamic changes in frequency, modulation index (MI) and load have been verified through tests. Power loss analysis was performed in PLECS software, and the efficiency was found to be 96.45%.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 7","pages":"4278-4294"},"PeriodicalIF":1.8,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Modular Expandable Multilevel Converter","authors":"Shuai Gao,&nbsp;Zhenyu Jiang,&nbsp;Fukuan Pang,&nbsp;Sixiang Zhao","doi":"10.1002/cta.4429","DOIUrl":"https://doi.org/10.1002/cta.4429","url":null,"abstract":"<div>\u0000 \u0000 <p>Multilevel converters are widely used because of low harmonic content, low switching loss, and low electromagnetic interference. However, when the output voltage level of the traditional multilevel converter is high, it needs many power semiconductors and the control is complicated. In order to solve this problem, a new type of expandable multilevel converter is proposed in this brief. It can achieve same number of output levels with a low switch count, and the topology can be changed to adjust the output of different numbers of voltage levels. Furthermore, the one-dimensional space vector modulation strategy for the proposed topology is designed to generate switching pulses, which significantly simplify the control burden. Finally, the experimental results are provided to verify the effectiveness of the proposed topology.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 7","pages":"4353-4358"},"PeriodicalIF":1.8,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AGORA: Adaptive Generation of Orthogonal Rational Approximations for Frequency-Response Data","authors":"Andria Lemus,&nbsp;Arif Ege Engin","doi":"10.1002/cta.4468","DOIUrl":"https://doi.org/10.1002/cta.4468","url":null,"abstract":"<p>This paper introduces the adaptive generation of orthogonal rational approximations (AGORA) method for rational function approximation of measured or simulated microwave network parameters. The output of AGORA is a state-space model or a rational function model that is representative of the input data. The generated model can then be used to interpolate the data or to evaluate the data quality. A typical application is the time-domain signal and power integrity analysis in circuit simulations using the generated model from measured or simulated interconnnects and power distribution networks. AGORA allows estimating the model order for a given error tolerance and does not require any initial estimates or adjustment of hyperparameters.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5751-5759"},"PeriodicalIF":1.6,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/cta.4468","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A High-Precision and Wide-Range DPFM/DPWM Generation Method Using FPGA","authors":"Fuchao Lu,&nbsp;Zheng-Quan Zhang","doi":"10.1002/cta.4444","DOIUrl":"https://doi.org/10.1002/cta.4444","url":null,"abstract":"<div>\u0000 \u0000 <p>Current digital pulse width modulation (DPWM) implementations prioritize high-precision duty cycle control, but they suffer from relatively lower frequency adjustment precision, which is inadequate for applications requiring high frequency resolution, such as RF Class-D power amplifiers. To address this limitation, this paper introduces a cost-effective FPGA-based method for generating multichannel high-precision and wide-range digital pulse frequency modulation (DPFM) signals. This method allows for the simultaneous generation of multiple adjustable duty cycle and frequency pulses, with precise control over the phase shift between different pulse channels. This solution innovatively enables high-precision regulation of both period and duty cycle across a broad frequency spectrum. It utilizes a hybrid architecture that integrates multiple counters with delay units, thus expanding the adjustable range for both cycle and duty cycle while preserving high precision. In this paper, employing IDELAYE2 as the delay unit, the PFM signals generated have a minimum frequency of 12 Hz and a maximum of 15 MHz, with all adjustments—period, duty cycle, and phase shift—achieving an accuracy of 39 ps. The scheme's validity is confirmed using the Xilinx ZYNQ XC7Z100 series FPGA, demonstrating an average deviation of approximately 6 ps between the nominal and actual measured values, linearity \u0000<span></span><math>\u0000 <msup>\u0000 <mi>R</mi>\u0000 <mn>2</mn>\u0000 </msup></math> = 0.9993.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5903-5912"},"PeriodicalIF":1.6,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TIA Design for FMCW LiDAR Systems","authors":"Amin Chegeni,&nbsp;Johannes Sturm","doi":"10.1002/cta.4465","DOIUrl":"https://doi.org/10.1002/cta.4465","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a design methodology for a transimpedance amplifier (TIA) that emphasizes enhanced power supply rejection ratio (PSRR), specifically tailored for long-distance frequency-modulated continuous-wave (FMCW) LiDAR systems. In these advanced systems, when critical components such as the transmitter, receiver, and optical phase shifters are integrated into a system-on-chip (SoC), the power supply is subject to significant fluctuations. These fluctuations primarily result from the high current switching activities inherent in these components. Given the extremely weak amplitude of the received optical signals, it is imperative that the TIA, serving as the initial stage of signal amplification, possesses a robust ability to reject variations in the power supply to maintain signal integrity. Another critical challenge in TIA design is the rejection of input DC current. Typically, the AC current signal, which carries the desired distance information, is accompanied by a substantial DC current. If left unaddressed, this DC component can saturate the TIA, thereby preventing the accurate amplification of the AC signal. To overcome this, the proposed TIA incorporates a mechanism specifically designed to reject the DC current, ensuring that the amplifier operates within its optimal range and effectively processes the weak AC signal. The proposed TIA architecture not only addresses the DC current rejection but also significantly improves the PSRR, making it highly suitable for the stringent demands of integrated LiDAR systems. Furthermore, the versatility of the proposed TIA design allows it to be applied in other systems that encounter similar challenges with power supply variations and input DC current interference. Detailed post layout simulations conducted using the 0.25-μm IHP standard CMOS process demonstrate that the proposed TIA achieves a substantial improvement in PSRR, with a 30-dB enhancement compared with conventional TIA designs. This performance is maintained even in the presence of input DC current, underscoring the efficacy of the proposed design in real-world applications. The results indicate that the proposed TIA design is a robust and efficient solution for SoC-based FMCW LiDAR systems and other applications requiring high sensitivity and resilience to power supply disturbances.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5739-5750"},"PeriodicalIF":1.6,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 80-MS/s 60.9-dB SNDR Fully Differential Ring Amplifier-Based SAR-Assisted Pipelined ADC With Dual Redundancy in 65-nm CMOS","authors":"Hao Chen,&nbsp;Mingchao Jian,&nbsp;Zhenyu Wang,&nbsp;Huanlin Xie,&nbsp;Bo Sun,&nbsp;Chunbing Guo","doi":"10.1002/cta.4442","DOIUrl":"https://doi.org/10.1002/cta.4442","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a single-channel, 12-bit, 80-MS/s SAR-assisted pipelined ADC. A ring amplifier is used as the inter-stage residue amplifier, employing dynamic biasing to enhance PVT stability. Additionally, the drain-source voltage of the MOS transistor is utilized to generate a dead-zone voltage, which reduces the impact on the secondary pole frequency and further improves stability. A non-binary weighted capacitor array is employed in the two-stage sub-ADC to provide redundancy, reduce settling time, improve speed, and work in conjunction with the common-mode stable switching timing. This approach solves the problem that traditional switching timing can only correct one-sided settling errors, thereby fully exploiting the redundancy's correction capability. The prototype ADC was fabricated in a 65-nm CMOS process and consumes 5.85 mW from a 1.1-V power supply at 80 MS/s. The SNDR and SFDR are 53.93 and 70.33 dB, respectively, with a Nyquist input, achieving a Walden figure-of-merit (FoM) of 179 fJ/conversion-step.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5862-5874"},"PeriodicalIF":1.6,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress-Relaxed Driver System Using Power-Delay Efficient Level Shifters for Compute-in-Memory Based on the Floating Gate Devices","authors":"Zhiguo Yu,&nbsp;Yating Dong,&nbsp;Yang Qiao,&nbsp;Zhengyuan Lin,&nbsp;Xuyuan Gu,&nbsp;Xiaofeng Gu","doi":"10.1002/cta.4463","DOIUrl":"https://doi.org/10.1002/cta.4463","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, a stress-relaxed driver system applied to compute-in-memory (CIM) is proposed for programming, reading and erasing of the CIM chip. The driver system utilizes a hierarchical regulation method to achieve accurate row and column selectivity, reducing the area overhead of the peripheral driver system for the CIM array. In order to suppress the voltage fluctuation of the power supply and ground caused by direct path currents, power-delay efficient positive and negative voltage level shifters are proposed. The proposed level shifters allows transistors used in the driver system to switch voltages at the safe operating limit. The driver system based on 1024 \u0000<span></span><math>\u0000 <mo>×</mo></math> 2048 floating gate devices is implemented using a 65-nm CMOS process. The driver system converts a 1.8-V voltage-domain input signal to a high-voltage-domain output voltage, which meets the requirements of operating transmissions from −10 to 9 V. The simulation results show that the maximum voltage stress in the driver system is less than 12 V, achieving a reduction of 21.9% compared to the previous study. Simultaneous switching of 256 word-lines can be achieved across the temperature range of −40°C to 125°C with a 2-pF capacitive load. The driver system can support the switching of the program, erase, and read modes. In the read mode, the delay remains less than 13 ns for the gate voltage of floating gate devices ranging from 3 to 7 V. We conducted the comparative analysis and simulations of the proposed level shifters to elucidate pertinent design trade-offs. The comparison results show that the proposed level shifters exhibit significant advantages in peak current and power consumption compared with the topologies of various level shifters and have the lowest power-delay product.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"5715-5728"},"PeriodicalIF":1.6,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparative Analysis Between Recursive Least Squares State Space (RLSS) and Nonlinear Least Squares (NLS) Methods for Parameter Identification in Buck Converters Applied to Solar Energy Systems","authors":"André Luiz Silva Crivellari,&nbsp;André Salume Lima Ferreira Leão,&nbsp;Bartolomeu F. dos Santos Junior,&nbsp;Roberto Francisco Coelho,&nbsp;Lenon Schmitz,&nbsp;Denizar Cruz Martins,&nbsp;Walbermark M. dos Santos","doi":"10.1002/cta.4459","DOIUrl":"https://doi.org/10.1002/cta.4459","url":null,"abstract":"<div>\u0000 \u0000 <p>The lifespan of a converter depends on the reliability of its components. In non-redundant designs like buck converters, a single component failure can shut down the circuit. Capacitors are most prone to failure compared to inductors and semiconductors. Monitoring parameters like equivalent series resistance, rather than relying on manual data, helps assess a converter's useful life. This article compares two parameter estimation methods: recursive state space and non-linear least squares. The R² value and residuals analysis ensure the results are reliable and correlate well with real converter values.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 10","pages":"6059-6074"},"PeriodicalIF":1.6,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145228154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}