International Journal of Circuit Theory and Applications最新文献_第4页

A 12-Bit 1-MS/s 14.96- μW SAR ADC With Improved True Single-Phase Clock Flip-Flops 具有改进的真单相时钟触发器的12位1 ms /s 14.96 μW SAR ADC

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2026-01-05 DOI: 10.1002/cta.70311

Chenglong Zhu, Haochuan Wang, Yu Xia, ChenKai Peng, Jiale Chen, KaiChen Yi, Hengzhi Hong, Mang I. Vai, Sio Hang Pun, Yuhua Cheng, Hui Hong

{"title":"A 12-Bit 1-MS/s 14.96-\u0000\u0000 μW SAR ADC With Improved True Single-Phase Clock Flip-Flops","authors":"Chenglong Zhu, Haochuan Wang, Yu Xia, ChenKai Peng, Jiale Chen, KaiChen Yi, Hengzhi Hong, Mang I. Vai, Sio Hang Pun, Yuhua Cheng, Hui Hong","doi":"10.1002/cta.70311","DOIUrl":"https://doi.org/10.1002/cta.70311","url":null,"abstract":"<div>\u0000 \u0000 <p>A low-power 12-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. The ADC employs segmented capacitive digital-to-analog converter (CDAC) array and improved true single-phase clock flip-flops (ITSPCFFs) to reduce power consumption and chip area. The proposed ITSPCFFs effectively block the potential leakage path inherent in conventional true single-phase clock flip-flops (TSPCFFs). A kickback noise–suppression technique is adopted in a fully dynamic comparator to improve ADC accuracy without additional power consumption. Fabricated in a 65-nm CMOS technology, the prototype achieves an ENOB of 10.9 bits and a SNDR of 67.2 dB at a 1-MS/s sampling rate. Operating at a 1-V supply voltage, the prototype consumes a total power consumption of 14.96-\u0000<span></span><math>\u0000 <mi>μ</mi></math>W and achieves a FoM of 7.8 fJ/conversion-step. The proposed SAR ADC features low-power consumption, high-energy efficiency, and compact area, making it well suited for systems on chip (SoCs).</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4482-4492"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dual-Mode Over-Modulation Strategy for a Two-Phase Hybrid Stepper Motor Fed by a Six-Switch Inverter 六开关逆变器两相混合式步进电机的双模过调制策略

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2025-12-31 DOI: 10.1002/cta.70285

Huan Shao, Yuxiang Xu, Huiying Chen, Wenlong Zhu, Yuepeng Zhao, Bangyang Wei

{"title":"Dual-Mode Over-Modulation Strategy for a Two-Phase Hybrid Stepper Motor Fed by a Six-Switch Inverter","authors":"Huan Shao, Yuxiang Xu, Huiying Chen, Wenlong Zhu, Yuepeng Zhao, Bangyang Wei","doi":"10.1002/cta.70285","DOIUrl":"https://doi.org/10.1002/cta.70285","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper addresses the limited voltage output capacity when a two-phase six-switch inverter is applied to a two-phase hybrid stepper motor and the issue of still insufficient voltage output capacity after applying a traditional over-modulation strategy based on the minimum phase error principle. It proposes a dual-mode over-modulation strategy by further subdividing the two regions of the conventional strategy and dynamically employing truncation or switching to fundamental voltage vectors based on phase angle. First, the expressions of the action time of adjacent basic vectors and the fundamental amplitude of output voltage are derived under both the traditional over-modulation strategy and the dual-mode over-modulation strategy. Second, the relationship between the reference voltage modulation ratio and both the output voltage modulation ratio and harmonic distortion rate is analyzed. Finally, a platform is built for simulation and experimental verification. Simulation and experimental results show that the proposed dual-mode over-modulation strategy improves the maximum output voltage modulation ratio from 0.958 to 1.041 compared to the traditional over-modulation strategy and improves the voltage utilization by 8.7%.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4641-4651"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Dual-Band Filtering Power Amplifier Based on Three-Line Coupled Structure 基于三线耦合结构的双带滤波功率放大器

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2026-01-05 DOI: 10.1002/cta.70303

Teng Wang, Yongle Wu, Xiaopan Chen, Zhuojia Yao, Weimin Wang

{"title":"A Dual-Band Filtering Power Amplifier Based on Three-Line Coupled Structure","authors":"Teng Wang, Yongle Wu, Xiaopan Chen, Zhuojia Yao, Weimin Wang","doi":"10.1002/cta.70303","DOIUrl":"https://doi.org/10.1002/cta.70303","url":null,"abstract":"<div>\u0000 \u0000 <p>This letter proposes a novel filter structure based on the three-line coupled structure (TLCS) and designs a dual-band filtering (DBF) power amplifier (PA) using this structure. The output matching network (OMN) of the PA integrates a suppressing network and a TLCS filter, delivering excellent filtering performance and effective out-of-band suppression. To validate the feasibility of the proposed structure, a dual-band filtered PA covering 2.4–2.8 GHz and 3.78–4.08 GHz was designed, fabricated, and measured. The measured peak drain efficiency (DE) values are 65.1% and 54.8%, respectively, with peak output power (P<sub>out</sub>) of 40.9 and 40.3 dBm. The measured fractional bandwidths (FBWs) of the two frequency bands are 15.4% and 7.6%. Compared with existing dual-band PA designs reported, the proposed PA has a wider passband bandwidth. Besides, using a 20-MHz long-term evolution (LTE) signal with a 7-dB peak-to-average power ratio (PAPR) and applying the digital predistortion (DPD), the adjacent channel power ratios (ACPRs) of the PA are −47.03 and −47.68 dBc, corresponding to the two frequency bands.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4580-4587"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

One-Octave Bandwidth-Tunable Filter Power Amplifier Based on Radial Stub Matching Network 基于径向短段匹配网络的单倍频带可调滤波器功率放大器

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2025-12-26 DOI: 10.1002/cta.70299

Ming Li, Minshi Jia, Zhiqun Cheng, Zhiwei Zhang, Senlei Liu, Jiankang Zhang

{"title":"One-Octave Bandwidth-Tunable Filter Power Amplifier Based on Radial Stub Matching Network","authors":"Ming Li, Minshi Jia, Zhiqun Cheng, Zhiwei Zhang, Senlei Liu, Jiankang Zhang","doi":"10.1002/cta.70299","DOIUrl":"https://doi.org/10.1002/cta.70299","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, a one-octave broadband filtering power amplifier (FPA) with bandpass filtering response is presented by utilizing a bandwidth-tunable bandpass filter (BPF) as the matching network (MN). Existing FPAs cannot achieve flexible bandwidth adjustments by changing only the circuit parameters. The MN structure incorporates the bandwidth (<i>θ</i><sub><i>c</i></sub>) as a variable in the closed-form equations of the bandpass filter prototype, enabling the flexible design of MNs with bandpass filtering response. The MN employed is of fixed order, and the bandwidth can be extended from narrowband to more than one octave by simplymodifying the impedance characteristics of the microstrip lines. Furthermore, this paper innovatively adopts quarter-wavelength radial stubs instead of conventional short-circuited branch lines in the bandpass filter prototype, which enhances both the bandwidth and efficiency of the power amplifier. To verify the theory, a bandpass FPA was fabricated capable of supporting over one-octave bandwidth (1.8–3.6 GHz), with measured drain efficiency ranging from 54% to 71% and output power varying from 39.3 to 41.7 dBm.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4551-4557"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 40.68-MHz Active Rectifier Using PLL and PWM Control of DC-DC Converter for ON/OFF Delay Compensation 采用锁相环和PWM控制的DC-DC变换器进行开/关延时补偿的40.68 mhz有源整流器

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2026-07-01 DOI: 10.1002/cta.70547

Woorim Lee, Sungmin Shin, Seongbin Kwon, Geonwoo Baek, Jongyeop Kim, Franklin Bien

{"title":"A 40.68-MHz Active Rectifier Using PLL and PWM Control of DC-DC Converter for ON/OFF Delay Compensation","authors":"Woorim Lee, Sungmin Shin, Seongbin Kwon, Geonwoo Baek, Jongyeop Kim, Franklin Bien","doi":"10.1002/cta.70547","DOIUrl":"https://doi.org/10.1002/cta.70547","url":null,"abstract":"<p>This paper presents a high-efficiency active rectifier design for implantable medical devices (IMDs), where size reduction and power efficiency are critical requirements. Operating at 40.68 MHz allows significant miniaturization of passive components but also introduces substantial challenges in compensating ON/OFF delays during the rectification process. These delays can cause inaccurate switching instances, leading to increased conduction loss and degraded system performance. To address this issue, this work proposes a ramp-based phase-locked loop (RPLL) architecture that merges the timing controllability of pulse-width modulation (PWM) techniques with the phase-tracking capability of a phase-locked loop. The proposed RPLL ensures accurate switching-phase alignment, compensates delay variations, and stabilizes the rectifier operation. As a result, the rectifier achieves improved power conversion efficiency (PCE) and voltage conversion ratio (VCR), enabling reliable operation under the stringent power constraints of IMDs. The circuit is implemented in a standard 0.18-μm CMOS process, ensuring manufacturability and low power consumption. Cadence simulation results demonstrate a peak PCE of 90.3% and a maximum VCR of 98.0%, verifying the effectiveness of the proposed architecture in high-frequency wireless power transfer applications.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4469-4481"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/cta.70547","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Dual Substrate Structure Self-Resonant Coil Is Used for Wireless Power Transfer System 一种用于无线电力传输系统的双衬底结构自谐振线圈

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2025-12-28 DOI: 10.1002/cta.70251

Benshang Su, Haokun Chi, Chunxiao Mu, Yongchao Hou

{"title":"A Dual Substrate Structure Self-Resonant Coil Is Used for Wireless Power Transfer System","authors":"Benshang Su, Haokun Chi, Chunxiao Mu, Yongchao Hou","doi":"10.1002/cta.70251","DOIUrl":"https://doi.org/10.1002/cta.70251","url":null,"abstract":"<div>\u0000 \u0000 <p>Traditional wireless power transfer (WPT) systems rely on compensation capacitors to achieve reactive power compensation. This approach not only increases the system size and cost but also may introduce reliability issues. In contrast, self-resonant wireless power transfer (SRWPT) systems realize resonance by utilizing the inherent parasitic capacitance of the coil, eliminating the need for additional capacitors. As a result, it offers distinct advantages of a simple structure and low cost. However, most existing studies focus on the megahertz (MHz) frequency band, while research addressing medium-power applications below 1 MHz remains relatively insufficient. This paper explores SRWPT systems, with an emphasis on applications operating at low resonant frequencies, and proposes a self-resonant coil featuring a split-type dual-substrate structure. Both electromagnetic simulations and experimental measurements confirm that the multilayer structural design significantly reduces the resonant frequency. The finite element method (FEM) is employed to perform simulation analysis on the coil, investigating the effects of key parameters—including coil width, turn spacing, and number of turns—on the coil's quality factor (Q). An optimized prototype of the coil is fabricated and tested. At a resonant frequency of 910 kHz, the coil achieves a quality factor of 25.8. A WPT system is constructed using the proposed self-resonant coil, yielding a DC-DC efficiency of 80%. This study provides an efficient and low-cost implementation solution for WPT systems operating in the medium- and low-frequency bands.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4616-4626"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Enhanced TPS Modulation Strategy With Full-Range ZVS for LCL-Type Resonant DAB Converter lcl型谐振DAB变换器全量程ZVS增强TPS调制策略

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2026-01-02 DOI: 10.1002/cta.70305

Song Hu, Zhiyi Zhou, Rui Wang, Chuan Sun, Yiwang Wang, Huiqing Wen, Wu Chen, Xiaodong Li

{"title":"An Enhanced TPS Modulation Strategy With Full-Range ZVS for LCL-Type Resonant DAB Converter","authors":"Song Hu, Zhiyi Zhou, Rui Wang, Chuan Sun, Yiwang Wang, Huiqing Wen, Wu Chen, Xiaodong Li","doi":"10.1002/cta.70305","DOIUrl":"https://doi.org/10.1002/cta.70305","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents an enhanced triple-phase shift (ETPS) modulation strategy for the inductor–capacitor–inductor (LCL) type resonant dual active bridge (DAB) converter. By analyzing the zero-voltage switching (ZVS) conditions and operating modes using fundamental harmonic approximation (FHA), the proposed ETPS strategy adaptively adjusts the phase shift angles to ensure ZVS across the full operational range, particularly over a wide voltage conversion range. Furthermore, for both buck and boost modes, the total root-mean-square (RMS) current is minimized using the Lagrange multiplier method (LMM) to reduce conduction losses. Closed-form analytical expressions for the optimal phase shift angles are derived to enable efficient power regulation. The effectiveness of the proposed strategy is validated through simulations and confirmed by experimental results, which demonstrate that the ETPS strategy consistently achieves ZVS under various load conditions and outperforms the conventional unity power factor (UPF)–triple-phase shift (TPS) strategy in terms of efficiency.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4652-4664"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A High Linear CMOS PA Using a Weighted Distributed Enhanced Transformer Phase-Delayed Group Linearizer at 77 GHz 基于加权分布式增强变压器相位延迟组线性器的77 GHz高线性CMOS放大器

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-09-04 Epub Date: 2026-01-01 DOI: 10.1002/cta.70301

Omar Z. Alngar

{"title":"A High Linear CMOS PA Using a Weighted Distributed Enhanced Transformer Phase-Delayed Group Linearizer at 77 GHz","authors":"Omar Z. Alngar","doi":"10.1002/cta.70301","DOIUrl":"https://doi.org/10.1002/cta.70301","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a W-band two-way four-stage power amplifier (PA) implemented in 28-nm CMOS technology, featuring a novel weighted distributed enhanced group linearizer (WDE-GL). The proposed WDE-GL architecture incorporates three stages, each operating at a different power level along the signal path. This design enables compensation with different weights for each linearizer stage, optimizing the linear performance, particularly for high-gain RF PAs. Each WDE-GL stage employs an introduced transformer phase-delayed reverse body-biasing technique to reduce its insertion loss and improve its compensation slope, achieving an optimal trade-off between linearity, efficiency, and gain. Furthermore, this approach supports stage-specific activation, providing flexibility for high-accuracy and eco-friendly modes, making it well-suited for automotive radar systems and electric vehicle applications. The implemented PA achieves, at 77 GHz, a maximum power added efficiency (PAE) of 11.7%, an output power at the 1-dB compression point (OP<sub>1dB</sub>) of 13.8 dBm, and a saturated output power (<i>P</i><sub>sat</sub>) of 15.7 dBm, utilizing a core area of 0.11 mm<sup>2</sup>. The WDE-GL significantly enhances the linear behavior of the PA, reducing the amplitude-to-amplitude, amplitude-to-phase, and intermodulation distortions. It also increases the OP<sub>1dB</sub> and its PAE by 3.4 dB and 4.5%, respectively. These improvements represent enhancements of 120% and 83% compared with the deactivated WDE-GL case, marking the best reported performance for W-band PAs.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 9","pages":"4558-4569"},"PeriodicalIF":1.4,"publicationDate":"2026-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148878255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Lyapunov Control Strategy for Full-Bridge Inverter-Based UPS Applications Using Load Current Estimator 负载电流估计器在全桥逆变器UPS应用中的Lyapunov控制策略

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-08-03 Epub Date: 2025-12-16 DOI: 10.1002/cta.70259

Ozan Gulbudak, Mustafa Gokdag, Burhan Hukumen

{"title":"Lyapunov Control Strategy for Full-Bridge Inverter-Based UPS Applications Using Load Current Estimator","authors":"Ozan Gulbudak, Mustafa Gokdag, Burhan Hukumen","doi":"10.1002/cta.70259","DOIUrl":"https://doi.org/10.1002/cta.70259","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a Lyapunov control method to regulate the uninterruptible power supply (UPS) dynamics. The single-phase full-bridge inverter is considered for UPS application, and the converter dynamics are controlled under unknown load conditions. UPS systems operate under specific output voltage characteristics. The current drawn from the UPS varies depending on the load connected to the UPS output. The model of the load is usually unknown, and the information for the load current is necessary to obtain a well-regulated closed-loop implementation. The Lyapunov control strategy uses the energy function to determine the control input. The determination of the control signal is based on the stability criterion of the Lyapunov control method; the selection of the control signal must ensure the asymptotic stability rule. However, the information on the load current is mandatory to achieve a fully regulated energy conversion operation. Thus, the load current is measured in most applications for simplicity. This paper proposes a Lyapunov control strategy using a model-based reference generator and load current observer. The proposed method uses the state observer to estimate the load current under unknown load conditions. The model-based reference generator produces the inductor current reference, and an inner Lyapunov regulator controls the inductor current. The mathematical concepts are verified using the real single-phase full-bridge prototype. The proposed control algorithm is implemented using STM32H743 digital signal processor (DSP). The performance of the Lyapunov regulator, load current estimator, and the model-based reference generator is experimentally investigated. According to the experimental results, the proposed control approach provides a robust and suitable UPS operation under unknown load conditions.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 8","pages":"4181-4194"},"PeriodicalIF":1.4,"publicationDate":"2026-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148662544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Temperature-Compensated Frequency-Locked Loop-Based RC Oscillator Featuring Single-Type Resistor Geometry Manipulation 一种基于温度补偿锁频环的RC振荡器，具有单型电阻几何操作

IF 1.4 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2026-08-03 Epub Date: 2025-12-22 DOI: 10.1002/cta.70258

Yimeng Wang, Yunbo Huang, Rui P. Martins, Yong Chen

{"title":"A Temperature-Compensated Frequency-Locked Loop-Based RC Oscillator Featuring Single-Type Resistor Geometry Manipulation","authors":"Yimeng Wang, Yunbo Huang, Rui P. Martins, Yong Chen","doi":"10.1002/cta.70258","DOIUrl":"https://doi.org/10.1002/cta.70258","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a temperature-compensated frequency-locked loop-based closed-loop oscillator featuring a novel process-scalable RC network composed of only a single type of resistor. In the proposed architecture, the dependence between the geometric parameters and temperature coefficient of a single-type resistor is exploited to implement a temperature-compensated RC network. A leakage-reduced analog-T switch is introduced to improve the frequency stability under high temperatures. In addition, a ping-pong switched-capacitor resistor is proposed to relax the trade-off between switching-induced voltage ripple and the size of the filtering capacitor. When fabricated in a 28 nm CMOS process, the prototype RC oscillator achieves a frequency error of 188.5 ppm/°C over the range −20°C to 100°C after compensation and an RMS period jitter of 9.51 \u0000<span></span><math>\u0000 <msub>\u0000 <mi>ps</mi>\u0000 <mi>rms</mi>\u0000 </msub></math>. The power efficiency is 0.89 μW/MHz.</p>\u0000 </div>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"54 8","pages":"4354-4370"},"PeriodicalIF":1.4,"publicationDate":"2026-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148662845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0