International Journal of Circuit Theory and Applications最新文献_第4页

Mathematical modeling and stress‐aware stability analysis of a nonideal multiport Single Inductor DC–DC converter for renewable energy 用于可再生能源的非理想多端口单电感直流-直流转换器的数学建模和应力感知稳定性分析

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-22 DOI: 10.1002/cta.4234

Ashutosh Gupta, Dheeraj Joshi

{"title":"Mathematical modeling and stress‐aware stability analysis of a nonideal multiport Single Inductor DC–DC converter for renewable energy","authors":"Ashutosh Gupta, Dheeraj Joshi","doi":"10.1002/cta.4234","DOIUrl":"https://doi.org/10.1002/cta.4234","url":null,"abstract":"This paper proposes a novel configuration for a multiport boost converter (MPBC) with a single inductor (SI), accounting for equivalent series resistances (ESRs) and minimizing input switching stress. The MPBC performance is evaluated and compared with other established topologies. The proposed MPBC interfaces two unidirectional input DC power ports and a rechargeable port for an energy storage element (ESE) with two output ports. The design integrates two renewable sources with the ESE as a third source. One output is for higher voltage, linked to a single‐phase inverter for AC loads. The other output is for lower DC voltage, used for DC loads. The configuration can be adjusted based on requirements. This converter has numerous applications in renewable energy systems, electric vehicles, and agriculture. The steady‐state and small signal modeling of MPBC has been done to derive the mathematical expressions for analyzing stability, stresses (both voltage and current), and performance considering ESRs. A 240 W, MPBC is fabricated along with improved switching strategies using DSP TMS320F28379D. Experimental and simulation results are compared to show the effectiveness of proposed scheme on stability, stresses, and efficient power transfer. Output power is regulated effectively by sharing the input power thereby reducing voltage stress on switches.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"10 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel high step‐up, low switching voltage stress DC‐DC converter using leakage inductance for resonant boosting 利用漏感实现谐振升压的新型高升压、低开关电压应力 DC-DC 转换器

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-19 DOI: 10.1002/cta.4236

Yin Chen, Haibin Li, Huaming Chen, Tao Jin

引用次数: 0

Variable‐order Caputo derivative of LC and RC circuits system with numerical analysis LC 和 RC 电路系统的变阶卡普托导数与数值分析

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-19 DOI: 10.1002/cta.4240

S Naveen, V Parthiban

引用次数: 0

Calibration on timing skew mismatch of time‐interleaved ADC based on optimized adaptive genetic algorithm back‐propagation neural network 基于优化自适应遗传算法反向传播神经网络的时间交错 ADC 时序偏移不匹配校准技术

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-19 DOI: 10.1002/cta.4252

Cheng Liu, Jiaqing Zhao, Yang Zhang, Zhennan Xi, Jiawei Deng, Xiangdong Luo

{"title":"Calibration on timing skew mismatch of time‐interleaved ADC based on optimized adaptive genetic algorithm back‐propagation neural network","authors":"Cheng Liu, Jiaqing Zhao, Yang Zhang, Zhennan Xi, Jiawei Deng, Xiangdong Luo","doi":"10.1002/cta.4252","DOIUrl":"https://doi.org/10.1002/cta.4252","url":null,"abstract":"Aiming to address the timing skew mismatch in the time‐interleaved analog‐to‐digital converter (TIADC) system, this paper presents a timing skew mismatch calibration method based on a back propagation (BP) neural network optimized by an adaptive genetic algorithm (AGA). In this paper, a trained BP neural network is used to detect the timing skew mismatch in the TIADC system, and the variable delay line is used to calibrate it. In this paper, AGA is used to optimize the BP neural network, accelerating its training speed and improving the detection accuracy of timing skew mismatch in the system. The proposed approach boasts superior detection speed and accuracy compared to other methods. In this paper, an 18‐bit 1GS/S 4‐channel TIADC system is simulated and the timing skew mismatch in the system is corrected. Simulation results show that the proposed calibration method has fast detection speed, high detection accuracy, and calibration accuracy. After completing the timing skew mismatch correction, the performance of the TIADC system is dramatically improved. The effective number of bits (ENOB) of the system increases by 9.5 bits, and the spurious‐free dynamic range (SFDR) increases by 59.9 dB.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"18 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High‐frequency digitally adaptive pulse skipping modulated voltage‐mode controlled quadratic buck converter 高频数字自适应脉冲跳变调制电压模式受控二次降压转换器

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-19 DOI: 10.1002/cta.4247

Vijay Kumar Gupta, Bipin Chandra Mandi

{"title":"High‐frequency digitally adaptive pulse skipping modulated voltage‐mode controlled quadratic buck converter","authors":"Vijay Kumar Gupta, Bipin Chandra Mandi","doi":"10.1002/cta.4247","DOIUrl":"https://doi.org/10.1002/cta.4247","url":null,"abstract":"The quadratic buck converter is renowned for its steep step‐down capability. It encounters increased losses due to its high component count. In scenarios with light loads, switching losses become the dominant factor. Additionally, the presence of two right‐half plane zeros impairs transient response, even at high‐frequency switching operations. Incorporating this converter into the digital domain introduces an undesired phenomenon known as subharmonic oscillation, rendering the system unstable, albeit potentially mitigated over time—a drawback particularly undesirable for converters tasked with rapid load dynamics. This paper introduces an adaptive pulse skipping modulation scheme to control metal–oxide–semiconductor field‐effect transistor (MOSFET) switching actions, enhancing overall efficiency in discontinuous conduction mode. Furthermore, the effects of right half‐plane (RHP) zeros on stability are analyzed within these switching schemes. The proposed scheme is integrated with voltage‐mode control. Simulation and theoretical analyses are conducted to validate this converter. A flat efficiency of 89% to 86% for the load range of 25 to 700 mA is obtained, outperforming other existing schemes. The results demonstrate that the adaptive pulse modulation scheme effectively improves efficiency and stability in discontinuous conduction mode converters. This research provides valuable insights for optimizing power electronics systems with varying load dynamics.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"384 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Systematic approach to improve performance of asymmetrical 21‐level inverter with fewer components 用更少的元件提高非对称 21 电平逆变器性能的系统方法

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-16 DOI: 10.1002/cta.4229

Madan Kumar Das, Priyatosh Mahish, Parusharamulu Buduma, Sukumar Mishra

{"title":"Systematic approach to improve performance of asymmetrical 21‐level inverter with fewer components","authors":"Madan Kumar Das, Priyatosh Mahish, Parusharamulu Buduma, Sukumar Mishra","doi":"10.1002/cta.4229","DOIUrl":"https://doi.org/10.1002/cta.4229","url":null,"abstract":"This paper proposes a systematic approach to enhance the performance of a 21‐level asymmetrical multilevel inverter (MLI) with less power electronics switches and DC voltage sources. In the first step (Configuration 1), the voltage level is improved at the cost of DC‐link voltage utilization. In the second step (Configuration 2), the ratio of the DC‐link voltages is modified to improve the utilization of DC‐link voltage, with an insignificant reduction of voltage levels as compared to Configuration 1. Finally, another modification of the MLI configuration is proposed (Configuration 3), by incorporating an H‐bridge in place of a T‐type module for further improvement of DC source utilization and increasing the number of voltage levels. Thus, Configuration 3 improves the inverter's total standing voltage (TSV) and efficiency. To reduce the number of DC sources, the output voltage levels are obtained in Configuration 3 by adding and subtracting the input DC sources. Moreover, conducting switches are reduced to minimize conduction loss and maximize efficiency. The DS1103‐based digital controller is used to verify the performance of the proposed configurations, which are compared with the literature‐based MLI models.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"50 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a Doherty power amplifier based on extended continuous class‐GF mode for broadband applications 为宽带应用设计基于扩展连续 GF 类模式的 Doherty 功率放大器

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-16 DOI: 10.1002/cta.4215

Xuefei Xuan, Zhiqun Cheng, Brendan Hayes, Zhiwei Zhang, Ziming Zhao, Tingwei Gong, Chao Le

{"title":"Design of a Doherty power amplifier based on extended continuous class‐GF mode for broadband applications","authors":"Xuefei Xuan, Zhiqun Cheng, Brendan Hayes, Zhiwei Zhang, Ziming Zhao, Tingwei Gong, Chao Le","doi":"10.1002/cta.4215","DOIUrl":"https://doi.org/10.1002/cta.4215","url":null,"abstract":"In this article, a systematic theory and design approach are presented to achieve bandwidth expansion of the Doherty power amplifier (DPA) by using extended continuous Class‐GF (ECCGF) power amplifiers (PAs) as carrier PAs. The results of the theoretical analysis indicate that compared to conventional DPA, introducing ECCGF PA as carrier PA into the DPA design can establish two larger target impedance spaces with overlapping regions for saturation and output back‐off (OBO) power levels, which can reduce the design complexity of impedance inverter networks (IINs) while achieving DPA bandwidth expansion. Based on this, the proposed design theory is validated in the design and fabrication of a prototype DPA employing the CGH40010F GaN HEMT provided by MACOM. The measured results show that under continuous wave excitation, the designed DPA delivers a saturated output power of 43.1–44.2 dBm in the range of 1.3–2.7 GHz with a relative bandwidth of 70%. The drain efficiencies of 61.2%–73.2% and 42.5%–52.7% are achieved over the entire band at the saturation and 6‐dB OBO power levels, respectively. The measured results also confirmed the theoretical findings.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"48 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling, design, and performance analysis of a Y‐source DC‐DC converter under limitations of hardware and leakage inductances 硬件和漏感限制下 Y 源 DC-DC 转换器的建模、设计和性能分析

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-16 DOI: 10.1002/cta.4243

Marcus V. M. Rodrigues, Rafael Santos, Luis De Oro Arenas, Fernando P. Marafão, Flávio A. S. Gonçalves

{"title":"Modeling, design, and performance analysis of a Y‐source DC‐DC converter under limitations of hardware and leakage inductances","authors":"Marcus V. M. Rodrigues, Rafael Santos, Luis De Oro Arenas, Fernando P. Marafão, Flávio A. S. Gonçalves","doi":"10.1002/cta.4243","DOIUrl":"https://doi.org/10.1002/cta.4243","url":null,"abstract":"The widespread of renewable energy sources often requires DC‐DC power converters with higher operational flexibility and voltage gain capability. The Y‐source converter offers significant features to fill this demand, but its performance can be negatively affected by coupled‐inductor leakage inductances. This paper presents simplified models for the Y‐source DC‐DC converter (YSDC) that, although not directly including the presence of leakage inductances, offer a satisfactory description of how the converter operates in terms of its steady‐state behavior, small‐signal dynamics, and estimation of power losses. These models allow for a comprehensive analysis of how non‐ideal components in the converter affect the determination of the YSDC voltage gain and efficiency and allow one to identify the most interesting design alternatives to satisfy the current and voltage stress constraints placed on the converter power switches, thus excluding undesired converter design alternatives. Experimental results with a 280 W real converter, using coupled‐inductor with leakage inductances, present results similar to those of switched circuit simulations and the derived models, thus confirming that the simplified models present satisfactory adherence to the real converter performance over the majority extent of the maximum duty cycle.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"124 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Input–output waveform engineered inverse Class F power amplifiers with high efficiency 输入输出波形工程设计的高效反向 F 类功率放大器

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-16 DOI: 10.1002/cta.4254

Zheming Zhu, Zhiqun Cheng, Minshi Jia, Kun Wang, Bingxin Li, Zhenghao Yang, Baoquan Zhong

引用次数: 0

Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design 考虑阈值电压的四输入低偏移 SA 实时位线漏电平衡电路，用于 SRAM 稳定性设计

IF 2.3 3区工程技术

International Journal of Circuit Theory and Applications Pub Date : 2024-08-15 DOI: 10.1002/cta.4248

Chunyu Peng, Wei Hu, Hao Zheng, Wenjuan Lu, Chenghu Dai, Xiulong Wu, Zhiting Lin, Junning Chen

引用次数: 0