A mm-Wave Power VCO and Frequency Doubler Based on Class-C Architecture Using 130 nm CMOS Technology

Abstract

This manuscript introduces a power voltage-controlled oscillator (PVCO) with a frequency doubler (FD), utilizing a complementary PMOS-NMOS architecture based on Class-C operation for millimeter-wave and fifth-generation (5G) systems. One output terminal of the VCO core is connected to a power stage operating at the fundamental frequency ( $f_o$) in the 21.2–23.2 GHz frequency band. The other output terminal is linked to a FD and a power stage working at the second harmonic frequency ( $2f_o$), covering the 42–46.5 GHz frequency range. All inductors are designed on-chip using HFSS simulation tools, achieving a high-quality factor, large self-resonance frequency (SRF), and small die area. To enhance the frequency sensitivity of the PVCO and FD-PVCO, every band is split into three sub-bands by manipulating only one-pin switching voltage. The PVCO operates in the 21.24–23.2 GHz range, achieving a figure of merit (FoM) equal to −194.5 dBc/Hz, a phase noise (PN) equal to −108 dBc/Hz, and a maximum output power ( $P_{\text{out}}$) equal to 5.74 dBm. Meanwhile, the FD-PVCO oscillates in the 42.48–46.4 GHz range, achieving a FoM of −200 dBc/Hz, a PN of −108 dBc/Hz, and an extreme $P_{\text{out}}=2.9\mathrm{dBm}$. The proposed design dissipates a DC-power equal to 2.4 mW and occupies an active area of 0.032 mm², whereas the overall chip size, including the pads, FD, and power stages, is 0.37 mm².