An 80-MS/s 60.9-dB SNDR Fully Differential Ring Amplifier-Based SAR-Assisted Pipelined ADC With Dual Redundancy in 65-nm CMOS

This paper presents a single-channel, 12-bit, 80-MS/s SAR-assisted pipelined ADC. A ring amplifier is used as the inter-stage residue amplifier, employing dynamic biasing to enhance PVT stability. Additionally, the drain-source voltage of the MOS transistor is utilized to generate a dead-zone voltage, which reduces the impact on the secondary pole frequency and further improves stability. A non-binary weighted capacitor array is employed in the two-stage sub-ADC to provide redundancy, reduce settling time, improve speed, and work in conjunction with the common-mode stable switching timing. This approach solves the problem that traditional switching timing can only correct one-sided settling errors, thereby fully exploiting the redundancy's correction capability. The prototype ADC was fabricated in a 65-nm CMOS process and consumes 5.85 mW from a 1.1-V power supply at 80 MS/s. The SNDR and SFDR are 53.93 and 70.33 dB, respectively, with a Nyquist input, achieving a Walden figure-of-merit (FoM) of 179 fJ/conversion-step.