Stress-Relaxed Driver System Using Power-Delay Efficient Level Shifters for Compute-in-Memory Based on the Floating Gate Devices

Abstract

In this paper, a stress-relaxed driver system applied to compute-in-memory (CIM) is proposed for programming, reading and erasing of the CIM chip. The driver system utilizes a hierarchical regulation method to achieve accurate row and column selectivity, reducing the area overhead of the peripheral driver system for the CIM array. In order to suppress the voltage fluctuation of the power supply and ground caused by direct path currents, power-delay efficient positive and negative voltage level shifters are proposed. The proposed level shifters allows transistors used in the driver system to switch voltages at the safe operating limit. The driver system based on 1024 $\times$ 2048 floating gate devices is implemented using a 65-nm CMOS process. The driver system converts a 1.8-V voltage-domain input signal to a high-voltage-domain output voltage, which meets the requirements of operating transmissions from −10 to 9 V. The simulation results show that the maximum voltage stress in the driver system is less than 12 V, achieving a reduction of 21.9% compared to the previous study. Simultaneous switching of 256 word-lines can be achieved across the temperature range of −40°C to 125°C with a 2-pF capacitive load. The driver system can support the switching of the program, erase, and read modes. In the read mode, the delay remains less than 13 ns for the gate voltage of floating gate devices ranging from 3 to 7 V. We conducted the comparative analysis and simulations of the proposed level shifters to elucidate pertinent design trade-offs. The comparison results show that the proposed level shifters exhibit significant advantages in peak current and power consumption compared with the topologies of various level shifters and have the lowest power-delay product.