FPGA-Based Resource-Optimal Approximate Multiplier for Error-Resilient Applications

Arithmetic units inspired by approximate computations have seen a significant development in error-resilient applications, wherein accuracy can be traded off for enhanced performance. Most of the existing literature pertaining to approximate computations targets ASIC platforms. In this paper, we focus on exploiting the features of approximate computation to design efficient digital hardware for FPGA platforms. Specifically, we propose an FPGA implementation of an approximate multiplier unit based on the CORDIC algorithm. Contemporary FPGA-based approximate multiplier implementations report a lot of compromise in accuracy and a relatively higher implementation cost in terms of utilized resources, timing, and energy. We conduct a detailed Pareto analysis to determine the number of optimal computing stages for the proposed CORDIC-based approximate multiplier that justifies the accuracy-performance trade-offs. More importantly, we focus on the optimal logic distribution of the proposed multiplier circuit by restructuring the top-level Boolean network and translating it into a circuit netlist that can be efficiently mapped onto the inherent FPGA fabric of LUTs and Carry4 primitives. Our CORDIC-based implementations significantly improve the accuracy metrics while maintaining a suitable performance trade-off. The efficacy of our proposed multiplier is tested using two image-processing applications, namely, image blending and image smoothening. The obtained results show a substantial improvement over the existing state-of-the-art approximate multipliers.