Symposium 1989 on VLSI Circuits最新文献_第6页

ALTICS: an advanced timing analysis system for VLSI ALTICS:一种先进的VLSI时序分析系统

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037467

H. Yamauchi, H. Sakuma, Y. Fujinami, K. Takamizawa

引用次数: 0

A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM 在4Mb CMOS EPROM中实现了一种新的交错虚拟地阵列架构

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037477

S. All, D. Nguyen, B. Sani, A. Shubat, C. Hu, Y. Me, R. Kazarounian, B. Eltan

引用次数: 7

A 50MHz 8Mb video RAM with a column direction drive sense amplifier 一个50MHz的8Mb视频RAM与一个列方向驱动感测放大器

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037511

H. Kotani, H. Akarnatsu, J. Matsushima, S. Okada, T. Shiragasawa, J. Houma, T. Yamada, M. Inoue

引用次数: 2

A monolithically integrated fiber-optic front-end receiver in GaAs Si technology GaAs Si技术中的单片集成光纤前端接收器

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037500

G. Nasserbakht, J. Adkisson, T. Kamins, B. Wooley, J. Harris

引用次数: 2

An experimental 27w 1Mb CMOS high-speed DRAM 实验性27w 1Mb CMOS高速DRAM

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037512

S. Dhong, W. Henkels, N. Lu, R. Scheuerlein, G. Brunner, K. Kitamura, V. Katavama, H. Niijima, T. Kirihata, R. Franch, W. Hwang, M. Nishiwaki, F. Pesavento, T. Rajeevakumar, Y. Sakaue, Y. Suzuki, E. Vañó

引用次数: 2

High performance BiCMOS circuit technology VLSI gate arrays 高性能BiCMOS电路技术VLSI门阵列

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037463

J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah

引用次数: 3

A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier 一种抑制16mbit DRAM感测放大器不对称特性的电路设计

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037513

H. Yamauchi, T. Yabu, T. Yamada, M. Inoue

引用次数: 1

Design of optically coupled three dimensional common memory for parallel processor system 并行处理器系统的光耦合三维公共存储器设计

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037499

M. Koyanagi, H. Takata, H. Mori, M. Hirose

{"title":"Design of optically coupled three dimensional common memory for parallel processor system","authors":"M. Koyanagi, H. Takata, H. Mori, M. Hirose","doi":"10.1109/VLSIC.1989.1037499","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037499","url":null,"abstract":"1 . I n t r o d u c t i o n The o p t i c a l l y c o u p l e d t h r e e d i m e n s i o n a l common memory ( c a l l e d 3D-OCC memory h e r e a f t e r ) i a a newly p roposed i n t e l l i g e n t memory f o r h i g h speed p a r a l l e l p r o c e s s i n g i n c o m p u t a t i o n [ l ] . Rapid t r a n s f e r of memory d a t a and t h e i r s i m u l t a n e o u s use by many CPU's are key i s s u e s f o r a c h i e v i n g u l t r a f a s t p a r a l l e l p r o c e s s i n g . The 3 D O C C memory i a a b l e t o t r a n s f e r a l a r g e b l o c k of d a t a w i t h v e r y h i g h speed by means of o p t i c a l c o u p l i n g in t h e v e r t i c a l d i r e c t i o n , v h i l e t h e c o n v e n t i o n a l memory o p e r a t i o n i s c a r r i e d o u t in t h e h o r i a o n t a l p l s n e . A l s o , s t o r e d d a t a i n t h e c o m m o n memory c a n b e a c c e s s e d by many p r o o e s s o r a v i t h o u t c o l l i s i o n . T h i s p a p e r d e s c r i b e 8 t h e d e a i g n methodology o f s u c h 3D-OCC memory w i t h t h e c a p a c i t y of 4 K b i t a x l b i t x 4 l a y e r s b a s e d on 2pm CMOS t e c h n o l o g y .","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125768352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

High-performance multiple-valued radix-2 signed-digit multiplier and its application 高性能多值基数-2符号数乘法器及其应用

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037521

S. Kawahitc, M. Kameyama, T. Higuchi

{"title":"High-performance multiple-valued radix-2 signed-digit multiplier and its application","authors":"S. Kawahitc, M. Kameyama, T. Higuchi","doi":"10.1109/VLSIC.1989.1037521","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037521","url":null,"abstract":"1. I \" 0 N In various VLSI systems for real-time applications, high-speed compact multipliers are required a s mcrocells. Signed-digit(SD) number representations are useful for such high-speed arithmetic circuits[l]. Since the SD number representation uses more than 3 values in each digit, we can expect the effective use of multiplevalued logic circuits for the compact harduare(VLS1) implementations. In particular, multiple-valued bidirectional current-mode circmits is essentially suitable. because frequently used linear summation including polarity can be performed by wiring[Z]. From the view point of compactness, the radix-4 SD number representation is attractive[31. For VLSI implementation, however, the radix-2 SD number( also called redundant binary number) representation is useful from the view points of stable and faster operation of multiple-valued current-mode circuits, if present VLSI process technology is directly used. In this paper, we describes high-speed compact radix-2 SO multiplier using multiple-valued current-mode logic circuits. A new tree structure of the SD multiplier using &-input addition of partial products are proposed. The current-mode wired summation can be fully used far the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed. 2. BIDIREcTlowAL -DE SD llRIllHZlTC CIRCUITS The radix-2 SD number system utilized here is a redundant representation using a symmetrical digit set(-1. 0.1). Addition of two numbers, X and Y are performed by the following successive steps in each digit. STEP 1: STEP 2: 2c; + Yi = z> zi = xi + yi","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126864781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Jitter analysis of high speed sampling systems 高速采样系统的抖动分析

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037506

M. Shinagawa, Y. Akazawa, T. Wakimoto

引用次数: 105