A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier

1) INTRODUCTlON Recently,lG-Mbit DRAMS have been designed and fabricated using submicron CMOS technology. However, the submicron MOSFETs with LDD or Efficient Punch through Stop (EPS) structure 111 have serious problems-such as 1) the drain current asymmetry, 2) the threshold voltage difference , and 3) the gatekource capacitance imbalance. [21[31 This is due to asymmetry of source and drain impurity profile caused by the shadowing of ion-beams by gate electrodes. This asymmetry has been reported to degrade the sensitivity of a DRAM sense amplifier com osed of LDD or EPS transistors.[31 I41 Several metRods to suppress the asymmetry effects using the oblique-rotating ion implantation technique have been proposed.[Z1[51 In this paper, we propose a novel circuit design to suppress the sense amplifier asymmetry effects not using the special process technique, and describe the e x p e r i m e n t a l r e s u l t s a b o u t t h e s e n s i t i v i t y improvement of the 16-Mbit DRAM sense amplifier by using the circuit design technique, and also compare with the values in case of using the obliquerotatin ion implantaion technique.