Symposium 1989 on VLSI Circuits最新文献

{"title":"Design of a CMOS token ring LAN controller, TRC, compatible with IEEE802.5 MAC protocol","authors":"T. Yaguchi, K. Fujimoto, E. Katsumata, K. Tanaka, K. Tamaru, A. Kanuma, Y. Katagiri, A. Nishikawa, H. Shiraishi, T. Yamamoto, K. Kimura, Y. Terui, T. Hamai","doi":"10.1109/VLSIC.1989.1037523","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037523","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A sub-ns clock josephson 4b processor","authors":"S. Kotani, T. Imamura, S. Hasuo","doi":"10.1109/VLSIC.1989.1037469","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037469","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126827030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Decoded-source sense amplifier for high-density DRAMs","authors":"J. Okamura, Y. Okada, M. Koyanagi, Y. Takeuchi, M. Yamada, K. Sakurai, S. Imada, S. Saito","doi":"10.1109/VLSIC.1989.1037510","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037510","url":null,"abstract":"The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V/sub cc/ of 4 V at 85 degrees C. >","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A data flow image compression processor","authors":"E. Kowashi, T. Uchimura, K. Neki, H. Hasegawa","doi":"10.1109/VLSIC.1989.1037518","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037518","url":null,"abstract":"This paper presents a binary image data compression and expansion processor that can compress 500 kbytes of image data into 35 kbyles of code data in 0.41 seconds. The pmessor equips with dala flow hardwax and CPU on the one chip. Topics described include the algorithms, anhifp.ture. and perfnmance. Visua-interface belween man and machine is of peat concern today. A large amount of imagc data has to he handled efficiently to imprwe this interface. For cxamplc, when an A4-sirc page of image is scanned at density of 200 pixelginch. the resultant image dam amouns to 500 kbyles. It takes so long as 7 minutes to !\"fer this by 9,600 bps MODEM. If requires one diskette to store this on a 2DD 3.5 inch floppy. In order to improve the efficiency, several coding schemes of compressing binary image data were recommended by the CCI'IT' 2. By applying one of the recommended methods, one page of image data can be compressed into 1/14. 35 kbytes of code data (Figure 1). Then one page of image can be transferred within 30 seconds. Thirteen pages of image can be stored on a floppy diskette. But another problem here is that it takes about 15 seconds for a multi-purpose processor to compress one page of image dab.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A versatile data-transfer control unit for a parallel processor system","authors":"Y. Nakakura, K. M. Sameky, Y. Tue, I. Okabayashi, M. Nakajima, S. Karino, K. Kaneko, H. Kadota","doi":"10.1109/VLSIC.1989.1037466","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037466","url":null,"abstract":"1. Intrdudirm VLSl parallel pmwssor system Is one of pmmlslng candldates for the future machine to carry out heavy-duty numerlcal computation. For the parallel system. not only PElprocessor element) operation speed but also Inter-PE data transfer Is very Important to achleve high performance. Especially. in the parallel processor system with localized memories and a connection network. there are two malor questions : \"haw to realize emcient data transfer between local memories wlth mlnlmum lnterference wlth PE operatlons.\" and \"how to assign the data In local memories? A new VLSI controller has been dmloped as a versatile data-transfcr control unR, X U , In a hlgh-prrfmmancc parallel pmccsor system : ADENAUI. The chtp gives some answers to the questions by the hardware. In this paper. the archltecture and the operations of TCU and the circults far the dedicated addrwslng block Address Generator are cxplalned. The chlp layout techniques are also discussed.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit","authors":"M. Usami, N. Shiozawa","doi":"10.1109/VLSIC.1989.1037464","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037464","url":null,"abstract":"In this contribution we would like to present a nev bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low P O Y ~ ~ per gate range of lnu/gste, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Enitter Coupled Logic) gates. INTRODUCTION The performance of high-speed bipolar gate arrays using ECL circuit technology is usually limited by LSI power dissipation. Lor-power NTL (Non -Threshold Logic) (1) ( 2 ) circuit has been developed for the bipolar high-packing density LSI's. In Hitachi. 5000-gate NTL gate arrays have been applied for supercomputer S-820 and large -scaled commercial computers (3) . High performance of NTL circuit is obtained by a linear amplifier like operation and a speed-up capacitance(Fig.1). But the driving capability of loading capacitances of the NTL circuits still depends on the output emitter follower current level, mhich is the reason not to decrease the power dissipation. SPL's design concept is based on how to overcome this NTL weak point. CIRCUIT CONCEPT AND OPERATION Table 1 summarizes the characteristics of SPL circuit. SPL has outstanding driving capability of 0.1311s / PF at law gate power compared rith the other circuit types as shorn in Fig.2. This merit of SPL is obtained by an AC coupled active push-pull circuit driven by the NTL inherent input inverter transistor, To improve the impulse response time, the base terminal of the output pull-doun transistor is biased by the low impedance emitter of the additonal clamp transistor. Fig.3 shovs the simulation data of the output voltage waveforms and the transient current waveforms in order to charge and discharge the heavy loading capacitances of 3pF. To keep the driving capability and save the power dissipation, a coupling capacitance C1 i n SPL has better be changed according to the loading capacitance CL. The pull-down transistor shortly turns off to be high impedance state, which enables output vired OR function features. PATH DELAY SIMULATION To show the high-speed operation of SPL. the tentative logic path propagation delay time r e s simulated as shown in Fig.5. The logic path of conventional IO-stage ECL gates including wired AND (collector dotting) and wired OR (emitter dotting) functions is converted to the one of equivalent 15-stage SPL gates. A single ECL wired AND gate is equal to double SPL NOR gates in tandem. In spite of this handicap, the path delay of SPL keeps advantage against the one of ECL on the condition of average loading wire capacitances of 0.57pF/gate. At the low power level of l m / g a t e , SPL shows high speed path delay of 3.3ns, which improves ECL gate delay of 9.1\"s by a factor of 2.75. Moreover, these SPL features sill be enhanced according to the transistor parameter progress especially of ft, Cte and rbb'. SPL rill be a brakthrough force of developing highpacking density and high-speed LSI's. APPL","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127042766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-reliability and high-speed design of 1Mb CMOS SRAM with 0.5/spl mu/m devices","authors":"S. Hayakawa, M. Kakumu, A. Aono, T. Yoshida, K. Sato, K. Noguchu, T. Ohtani, T. Nakayama, T. Asami, S. Morita, M. Kinugawa, J. Matsunaga, K. Ochit","doi":"10.1109/VLSIC.1989.1037474","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037474","url":null,"abstract":"1. Inboduetiao A 13- 1Mb CMOS SRAM fabricated with uipk polysilicon, double metal layers and 0.5~ gate MOS FET's will be described. The RAM utilizes the divided double-word-line scheme and three stage sense ampli6ers for high-speed operation. MMWV~L performance of the RAM is enhanced by 0.5~ MOS devices fully used in the internal circuits. An on-chip voltage down converter ( VDC ) is well designed to supply the inled VCC of 3.3V and to maintain lhe nliability of 0.5~ devices at external 5V operation.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121640661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analog-to-digital converter with non-linear capacitor compensation","authors":"R. Hester, K. Tan, M. De Wit, J. Fattaruso, S. Kiriaki, F. Tsay, Ç. Kaya, J. Paterson, H. Tigelaar","doi":"10.1109/VLSIC.1989.1037487","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037487","url":null,"abstract":"One of the sources of non-linearity in charge-redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. This paper will discuss Circuit techniques l o eliminate conversion errors caused by the capacitor voltage dependence, and performance data from circuits realized in a linear CMOS process will be presented. bv Cawsilor Voltaoe DBoendence The dependence of capacitance on voltage can be expressed by (1) where V represents the potential differsnce between the capacitor plates 111. Depending upon the capacitor plate and dielectric materials and the dielectric thickness, the linear coefficient. CI, can vary from 10s to 100s parts per million per volt. The quadratic coefficient, Cp, is typically much smaller. rarely exceeding 10 ppmlvolt2. The schematic diagram of a single-ended chargeredistribution capacitor array is shown in Figure 1. Its operation accomplishes both the sample-and-hold and successive approximation functions. When sampling the analog input signal, the top plate common to all capacitors is charged to VRS while the bottom plates are charged to VIN. When the sampling switches open, successive approximation Is executed connecting the bottom plates of the capacitors to either of two ievels. usually a reference voltage VREF and ground. Upon completion. the common lop piate node will return to VRS. It can be shown that the conversion error caused by capacitor voltage dependence can be expressed as c = CO I1 + c,v + C2V2), ~ ~ l N ~ ~ v l N ~ v R E F ~ ~ c l 12+C2VRS +[VIN+VREFl[%/31). (2) Typically, CMOS ADCs up lo 10-bit resolution are implemented in the single-ended topology of Figure 1. and voltage coefficients up l o 800 ppmlvolt can be tolerated. Beyond IO-bit resolution, fully-differential topologies are used. This architecture provides substantial improvements in noise immunity as well as an important extra degree of freedom in the sample-and-hold operation that is exploited in this work. The fully-differential architecture is composed of two identical capacitor arrays. During sampling, the top plates of bcth arrays are charged to VsAM, while the bottom plates of one array are charged lo VIN+ and those of the other array are charged to VIN~. During successive approximation, the bottom plates are connected either to VREF or ground as in the single ended case. When a particular capacitor in one array is connected to VREF. the corresponding capacitor in the other array is connected to ground. Completion of conversion leaves both top plates at potential, VT. The error of the fullydifferential ~ t r ~ ~ t ~ l e can be expressed by (c1 VINO/z) (2VT-VREF+(VSAM-V,,+)2.(vSAM~vlN~)z) + (31 +(CZVIND/3) (vT3-(vT-vREF)3 +(VSAM-VIN+)3-(vSAM-VlN-)3) 3 where VINO = VIN+ VI,.. Linear V . . The term involving C1 vanishes when the sampling and successive approximation are executed such that ZVT = V w andVW = (VIN++VIN.)12. In this case, equation (3) reduces to Figure 2 shows a schematic diagram of a circuit accomplishing this","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130947061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A multi bit test trigger circuit for Mbit SRAM's","authors":"F. Miyaji, T. Emort, Y. Matsuyama, Y. Kanaishi, K. Senoh, Y. Hagiwara","doi":"10.1109/VLSIC.1989.1037497","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037497","url":null,"abstract":"In recent years, the memory bit density of SRAM's becomes higher and higher. On the other hand, the testing time which is composed of DC parametric and AC functional tests becomes longer and longer. The AC test time increases in proportion to the memory bit density vhen N-test patterns are used. Therefore, the testing time of 4Mb SRAM is quadruple compared with that of 1Mb SRAM's in the case of the same bit organizations. It is very serious problem to spend long testing time in mass production. Therefore, the test modes for reduction of the testing time have been developed 111-[3l. But Multi Bit Test (MET) trigger circuit for SRAM's has not been developed in the case of the no extra NC (Non Connection)pin package. This paper will present a MBT trigger circuit for Mbit SRAH's having no extra NC pin package.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A TV(UHF/VHF)/Fm/AM compatible Bi-CMOS 1GHz single chip PLL IC","authors":"Y. Sugimoto, S. Mizoguchi, T. Matsuyama, J. Sano, H. Nakayama, M. Taguchi","doi":"10.1109/VLSIC.1989.1037505","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037505","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117346163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}