SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit

In this contribution we would like to present a nev bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low P O Y ~ ~ per gate range of lnu/gste, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Enitter Coupled Logic) gates. INTRODUCTION The performance of high-speed bipolar gate arrays using ECL circuit technology is usually limited by LSI power dissipation. Lor-power NTL (Non -Threshold Logic) (1) ( 2 ) circuit has been developed for the bipolar high-packing density LSI's. In Hitachi. 5000-gate NTL gate arrays have been applied for supercomputer S-820 and large -scaled commercial computers (3) . High performance of NTL circuit is obtained by a linear amplifier like operation and a speed-up capacitance(Fig.1). But the driving capability of loading capacitances of the NTL circuits still depends on the output emitter follower current level, mhich is the reason not to decrease the power dissipation. SPL's design concept is based on how to overcome this NTL weak point. CIRCUIT CONCEPT AND OPERATION Table 1 summarizes the characteristics of SPL circuit. SPL has outstanding driving capability of 0.1311s / PF at law gate power compared rith the other circuit types as shorn in Fig.2. This merit of SPL is obtained by an AC coupled active push-pull circuit driven by the NTL inherent input inverter transistor, To improve the impulse response time, the base terminal of the output pull-doun transistor is biased by the low impedance emitter of the additonal clamp transistor. Fig.3 shovs the simulation data of the output voltage waveforms and the transient current waveforms in order to charge and discharge the heavy loading capacitances of 3pF. To keep the driving capability and save the power dissipation, a coupling capacitance C1 i n SPL has better be changed according to the loading capacitance CL. The pull-down transistor shortly turns off to be high impedance state, which enables output vired OR function features. PATH DELAY SIMULATION To show the high-speed operation of SPL. the tentative logic path propagation delay time r e s simulated as shown in Fig.5. The logic path of conventional IO-stage ECL gates including wired AND (collector dotting) and wired OR (emitter dotting) functions is converted to the one of equivalent 15-stage SPL gates. A single ECL wired AND gate is equal to double SPL NOR gates in tandem. In spite of this handicap, the path delay of SPL keeps advantage against the one of ECL on the condition of average loading wire capacitances of 0.57pF/gate. At the low power level of l m / g a t e , SPL shows high speed path delay of 3.3ns, which improves ECL gate delay of 9.1"s by a factor of 2.75. Moreover, these SPL features sill be enhanced according to the transistor parameter progress especially of ft, Cte and rbb'. SPL rill be a brakthrough force of developing highpacking density and high-speed LSI's. APPLICATION The SPL circuit design concept rill be expanded to many high performance LSI circuit applications ouch as ultra large scale high -speed gate arrays. ASIC LSI's and so on. Noise problems caused by NTL like operation circuit rill be solved by the LSI-input noise-immunity circuits and the precise voltage generation circuits in LSI chips. One of the typical SPL circuit applications is shorn in Fig.6 for useful bus driver structure driving a large capacitance load. SPL wired OR features will enable to realize low -power high -speed bus driver. ACKNOYLEDGElENTS The authors uould like to thank N.Tanaka and A.Anzai. Device Development Center of Hitachi, Ltd. far their encouragements and advices. REFERENCES (1) H.Mukai, T.Suda and H.Kindo. "NTL -LSI Circuit Design Consideration" , Rev. Electr. Commun. Lab.. NTT, Tokyo, Sept.-Oct.. 1913 ( 2 ) M.Suruki, S.Horiguchi and T.Sudo, " A 5000 Gate Bipolar Masterslice LSI rith 500 ps Loaded Gate Delay". ISSCC Tech. Dig., Feb.. 1983 (3) n.Usami. S.Hososaka, A.Anrai, K.Otsuka, A . Masaki, S.E(urata, l.Ura and n.Nakagara, "status and Prospects for Bipolar ECL Gate Arrays", ICCD. Oct.. 1983