S. Hayakawa, M. Kakumu, A. Aono, T. Yoshida, K. Sato, K. Noguchu, T. Ohtani, T. Nakayama, T. Asami, S. Morita, M. Kinugawa, J. Matsunaga, K. Ochit
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High-reliability and high-speed design of 1Mb CMOS SRAM with 0.5/spl mu/m devices
1. Inboduetiao A 13- 1Mb CMOS SRAM fabricated with uipk polysilicon, double metal layers and 0.5~ gate MOS FET's will be described. The RAM utilizes the divided double-word-line scheme and three stage sense ampli6ers for high-speed operation. MMWV~L performance of the RAM is enhanced by 0.5~ MOS devices fully used in the internal circuits. An on-chip voltage down converter ( VDC ) is well designed to supply the inled VCC of 3.3V and to maintain lhe nliability of 0.5~ devices at external 5V operation.
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