Decoded-source sense amplifier for high-density DRAMs

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI:10.1109/VLSIC.1989.1037510

J. Okamura, Y. Okada, M. Koyanagi, Y. Takeuchi, M. Yamada, K. Sakurai, S. Imada, S. Saito

引用次数: 11

Abstract

The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V/sub cc/ of 4 V at 85 degrees C. >

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用于高密度dram的解码源感测放大器

讨论了用于高速、高密度dram的译码源感测放大器(DSSA)。为了防止位线放电电流引起感测放大器的共源节点箝位，DSSA有一个额外的锁存晶体管，其门由列解码器控制。DSSA已成功安装在4mb DRAM中，并在85℃时，在4 V/sub / V电压下提供了60 ns的RAS访问时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Symposium 1989 on VLSI Circuits

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