Analog-to-digital converter with non-linear capacitor compensation

One of the sources of non-linearity in charge-redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. This paper will discuss Circuit techniques l o eliminate conversion errors caused by the capacitor voltage dependence, and performance data from circuits realized in a linear CMOS process will be presented. bv Cawsilor Voltaoe DBoendence The dependence of capacitance on voltage can be expressed by (1) where V represents the potential differsnce between the capacitor plates 111. Depending upon the capacitor plate and dielectric materials and the dielectric thickness, the linear coefficient. CI, can vary from 10s to 100s parts per million per volt. The quadratic coefficient, Cp, is typically much smaller. rarely exceeding 10 ppmlvolt2. The schematic diagram of a single-ended chargeredistribution capacitor array is shown in Figure 1. Its operation accomplishes both the sample-and-hold and successive approximation functions. When sampling the analog input signal, the top plate common to all capacitors is charged to VRS while the bottom plates are charged to VIN. When the sampling switches open, successive approximation Is executed connecting the bottom plates of the capacitors to either of two ievels. usually a reference voltage VREF and ground. Upon completion. the common lop piate node will return to VRS. It can be shown that the conversion error caused by capacitor voltage dependence can be expressed as c = CO I1 + c,v + C2V2), ~ ~ l N ~ ~ v l N ~ v R E F ~ ~ c l 12+C2VRS +[VIN+VREFl[%/31). (2) Typically, CMOS ADCs up lo 10-bit resolution are implemented in the single-ended topology of Figure 1. and voltage coefficients up l o 800 ppmlvolt can be tolerated. Beyond IO-bit resolution, fully-differential topologies are used. This architecture provides substantial improvements in noise immunity as well as an important extra degree of freedom in the sample-and-hold operation that is exploited in this work. The fully-differential architecture is composed of two identical capacitor arrays. During sampling, the top plates of bcth arrays are charged to VsAM, while the bottom plates of one array are charged lo VIN+ and those of the other array are charged to VIN~. During successive approximation, the bottom plates are connected either to VREF or ground as in the single ended case. When a particular capacitor in one array is connected to VREF. the corresponding capacitor in the other array is connected to ground. Completion of conversion leaves both top plates at potential, VT. The error of the fullydifferential ~ t r ~ ~ t ~ l e can be expressed by (c1 VINO/z) (2VT-VREF+(VSAM-V,,+)2.(vSAM~vlN~)z) + (31 +(CZVIND/3) (vT3-(vT-vREF)3 +(VSAM-VIN+)3-(vSAM-VlN-)3) 3 where VINO = VIN+ VI,.. Linear V . . The term involving C1 vanishes when the sampling and successive approximation are executed such that ZVT = V w andVW = (VIN++VIN.)12. In this case, equation (3) reduces to Figure 2 shows a schematic diagram of a circuit accomplishing this. A resistor divider is used to derive the common-mode input signal from the differential inputs. During sampling, the top plates of both arrays are charged to this common-mode voltage. causing VINoR to appear across the upper array and -VIND/~ across the lower array. Shown in the figure is an optional unity gain buffer that can be used when the sampling speed is imporlant. Successive approximation begins when all switches, Ok, are closed and the MSB (sign bit) is determined. Notice that the ON and lN (MSB) switches are connected to the V R ~ ~ and ground buses differently than all other Ok and l k switches. This allows bipolar input signals and adds V, # common-mode signal to the tap plates. This common-mode level remains for the duration of the conversion, leaving VT=VREF/2 as desired. In addition to cancellation of the linear voltage coefficient. another important advantage of this sampling method is that the common-mode voltage presented to the comparator remains independent of the input common-mode voltage. This relaxes the common-mode rejection requirement of the comparator. Figure 3 shows a simulated error function of WO AOCs. They differ only in the way the signal is sampled. In one, VSIYII=VREF/2. and in the other VsAM=(vIN++VIN.)/2. The voltage coefficeints used in the simulation correspond l o the capacitors used in the fabrication of the ADC in Figure 4. Figure 4 shows the error function of an experimental 13-bit converter employing this sampling technique. The severe error at V,O= -VREF in Figure 3 is clearly absent in Figure 4. (c2/1 2)(vIND)(vREFz. VINO') (4) J E m nat on of OLaafat c Vo m e COWhen the samp ng memoo oescrsbed awve S employed. converter linearity to 15 bits can be achieved. Greater than 15bit linearity will require quadratic voltage coefficienf correction. This is accomplished by adding a signal. to the input during sampling. The variable. G. is an adjustable gain factor that allows compensation over a range at C2 values. A calibration algorithm is executed to determine the optimal value of G l o cancel the error signal given in equation (4). The hardware required to implement this correction consists of a separate correction capacitor array attached l o the top plates of the main capacitor array. nonlinear function generator, and a digital register to store the value of G and control the correction array. The function generator produces a signal proportional to V l N O ( V ~ ~ ~ z V ~ ~ ~ 2 ) that is sampled onto a fraction of the special array when the input signal is sampled. The fraction is determined by the G register. After sampling. the bonom plates of this special array are connected to VRE~IP, and it effectively becomes a parasitic capacitance during the successive approximation. The ~vsrall result is that a small amount of charge is added to the the signal charge to