A multi bit test trigger circuit for Mbit SRAM's

Abstract

In recent years, the memory bit density of SRAM's becomes higher and higher. On the other hand, the testing time which is composed of DC parametric and AC functional tests becomes longer and longer. The AC test time increases in proportion to the memory bit density vhen N-test patterns are used. Therefore, the testing time of 4Mb SRAM is quadruple compared with that of 1Mb SRAM's in the case of the same bit organizations. It is very serious problem to spend long testing time in mass production. Therefore, the test modes for reduction of the testing time have been developed 111-[3l. But Multi Bit Test (MET) trigger circuit for SRAM's has not been developed in the case of the no extra NC (Non Connection)pin package. This paper will present a MBT trigger circuit for Mbit SRAH's having no extra NC pin package.