A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM

Abstract

A new a r ray a r c h l t e c t u r e I s Introduced which I s s u l t a b l e f o r very h lgh dens l t y €PROMS. For a g lven se t o f deslgn r u l e s , t h l s approach y l e l d s 40% Smaller a r r a y size compared t o Drevlous a r r a y a rch l tec tu res . The Staggered V l r t u a l Ground (SVG) a r ray has been Implemented based on the sp l I t gate EPROM technology. A dual f unc t l on column muxlng scheme and Address T r a n s l t f o n Detec t lon deslgn techniques have been used t o achleve a 90nS 4Mb EPROM. The d l e size I s 7.6mn x 6 . 5 m and has been f a b r l c a t e d I n a 1.25um CMOS technology.