S. All, D. Nguyen, B. Sani, A. Shubat, C. Hu, Y. Me, R. Kazarounian, B. Eltan
{"title":"在4Mb CMOS EPROM中实现了一种新的交错虚拟地阵列架构","authors":"S. All, D. Nguyen, B. Sani, A. Shubat, C. Hu, Y. Me, R. Kazarounian, B. Eltan","doi":"10.1109/VLSIC.1989.1037477","DOIUrl":null,"url":null,"abstract":"A new a r ray a r c h l t e c t u r e I s Introduced which I s s u l t a b l e f o r very h lgh dens l t y €PROMS. For a g lven se t o f deslgn r u l e s , t h l s approach y l e l d s 40% Smaller a r r a y size compared t o Drevlous a r r a y a rch l tec tu res . The Staggered V l r t u a l Ground (SVG) a r ray has been Implemented based on the sp l I t gate EPROM technology. A dual f unc t l on column muxlng scheme and Address T r a n s l t f o n Detec t lon deslgn techniques have been used t o achleve a 90nS 4Mb EPROM. The d l e size I s 7.6mn x 6 . 5 m and has been f a b r l c a t e d I n a 1.25um CMOS technology.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM\",\"authors\":\"S. All, D. Nguyen, B. Sani, A. Shubat, C. Hu, Y. Me, R. Kazarounian, B. Eltan\",\"doi\":\"10.1109/VLSIC.1989.1037477\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new a r ray a r c h l t e c t u r e I s Introduced which I s s u l t a b l e f o r very h lgh dens l t y €PROMS. For a g lven se t o f deslgn r u l e s , t h l s approach y l e l d s 40% Smaller a r r a y size compared t o Drevlous a r r a y a rch l tec tu res . The Staggered V l r t u a l Ground (SVG) a r ray has been Implemented based on the sp l I t gate EPROM technology. A dual f unc t l on column muxlng scheme and Address T r a n s l t f o n Detec t lon deslgn techniques have been used t o achleve a 90nS 4Mb EPROM. The d l e size I s 7.6mn x 6 . 5 m and has been f a b r l c a t e d I n a 1.25um CMOS technology.\",\"PeriodicalId\":136228,\"journal\":{\"name\":\"Symposium 1989 on VLSI Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1989 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1989.1037477\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037477","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
A ar ar新雷c h l t e c t u r e s I Introduced哪种美国洛杉矶t b h l e f o r非常lgh穴l t y€PROMS。对于一个人来说，这是不可能的。Staggered V l r r u Ground (SVG)有一段r ray根据sp . I t gate EPROM technology推出。一个反f的f我的尺寸是7。6×6。5米，一直是联邦调查局的技术。
A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM
A new a r ray a r c h l t e c t u r e I s Introduced which I s s u l t a b l e f o r very h lgh dens l t y €PROMS. For a g lven se t o f deslgn r u l e s , t h l s approach y l e l d s 40% Smaller a r r a y size compared t o Drevlous a r r a y a rch l tec tu res . The Staggered V l r t u a l Ground (SVG) a r ray has been Implemented based on the sp l I t gate EPROM technology. A dual f unc t l on column muxlng scheme and Address T r a n s l t f o n Detec t lon deslgn techniques have been used t o achleve a 90nS 4Mb EPROM. The d l e size I s 7.6mn x 6 . 5 m and has been f a b r l c a t e d I n a 1.25um CMOS technology.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
