J. Gallia, A. Yee, K. Chau, I. Wang, W. Davis, K. Moore, B. Chas, C. Lemonds, R. Eklund, R. Havemann, T. Bonifield, J. Graham, J. Pozadzides, A. Shah
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High performance BiCMOS circuit technology VLSI gate arrays
BiCMOS circuits have been shown to be particularly attractive lor gate array applications because 01 ECL I/O and the high on-chip capacitance drive capabilnies. Full BiCMOS gate arrays have been introduced with densities up to 20k gates11.2.sl. However, due to bipolar size constraints, higher density arrays have been restricted to CMOS wre with BiCMOS used only in the periphery of the wre and lor ECLmL 1/0.[41
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