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Symposium 1989 on VLSI Circuits最新文献

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11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM's with voltage- and temperature-compensated interfaces 11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM，具有电压和温度补偿接口
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037493
Y. Urakawa, M. Matsui, A. Suzuki, N. Urakawa, K. Sato, T. Hamano, H. Kato, K. Ochri
{"title":"11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM's with voltage- and temperature-compensated interfaces","authors":"Y. Urakawa, M. Matsui, A. Suzuki, N. Urakawa, K. Sato, T. Hamano, H. Kato, K. Ochri","doi":"10.1109/VLSIC.1989.1037493","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037493","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130761380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 36μa 4MB PSRAM with quadruple array operation 36μa 4MB PSRAM，具有四组阵列操作
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037498
K. Kennnizaki, M. Ogata, T. Mochizuki, S. Kubono, T. Kazimoto, Y. Shimbo, K. Sato, O. Minato
{"title":"A 36μa 4MB PSRAM with quadruple array operation","authors":"K. Kennnizaki, M. Ogata, T. Mochizuki, S. Kubono, T. Kazimoto, Y. Shimbo, K. Sato, O. Minato","doi":"10.1109/VLSIC.1989.1037498","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037498","url":null,"abstract":"I, In t roduc t i on Recently, P S ~ U ~ O s t a t i c RAH CllC21 (PSRAH) c l i i ~ ~ have been used w i d e l y i n m a i l wstems such as personal computers and p r i n t e r bu f fe rs . Since PSRAH uses a dynamic type of memory cell which cons is t s of one HOS t r ans i s to r and one CaPacitor. i t needs a per iod i c re f resh cyc le to re1,ain data. Because i t i s ex t rese ly d e s i r a b l e f o r PSRAn t o act as i f i t i s S R A I I , t h i s p e r i o d i c re f resh cyc le has to be c a r r i e d aut au tomat i ca l l y by the PSRA'I i t s e l f . Th is re f resh mode is c a l l e d s e l f r e f r e s h mode. In s e l f node. a IOW power d i s s i p a t i o n i s essential because t he c h i p v i l i r e q u i r e bat tery 'backup i n standby node. However. the sore nenory d e n s i t y increases, to I H b i t s , f o r i ns tance . t he h isher the power d i r s i P a t i o n becomes.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115584664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High reliability CMOS SRAM with built-in soft defect detection 内置软缺陷检测的高可靠性CMOS SRAM
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037496
C. Koo, T. Toms, J. Jelemensky, E. Carter, P. Smith
{"title":"High reliability CMOS SRAM with built-in soft defect detection","authors":"C. Koo, T. Toms, J. Jelemensky, E. Carter, P. Smith","doi":"10.1109/VLSIC.1989.1037496","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037496","url":null,"abstract":"circuit technique that detects all possible process defects which may cause data retention or non-static failures in a CMOS SRAM array. The technique, dubbed Soft defect detection (SDD), can accomplish the 100% static test, that was unachievable previously, in milliseconds to assure perfect data retention without relying on high temperature hake. The SDD technique has been successfully implemented into the 16K bit SRAM module of a new 32 bit microcontroller. This paper will describe a newly developed","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells 具有模拟开关电流单元的8位100 MHz 3通道CMOS DAC
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037488
T. Matsuura, M. Ban, T. Tsukada, S. Ueda, H. Sato
{"title":"An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells","authors":"T. Matsuura, M. Ban, T. Tsukada, S. Ueda, H. Sato","doi":"10.1109/VLSIC.1989.1037488","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037488","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An expermental 16Mb DRAM with reduced peak-current noise 具有降低峰值电流噪声的实验性16Mb DRAM
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037515
Daeje Chin, Changhyun Kim, Y. Choi, D. Min, H. Hwang, Hoon Choi, S. Cho, T. Chung, C. Park, Y. Shin, Kwangpyuk Suh, Y. E. Park
{"title":"An expermental 16Mb DRAM with reduced peak-current noise","authors":"Daeje Chin, Changhyun Kim, Y. Choi, D. Min, H. Hwang, Hoon Choi, S. Cho, T. Chung, C. Park, Y. Shin, Kwangpyuk Suh, Y. E. Park","doi":"10.1109/VLSIC.1989.1037515","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037515","url":null,"abstract":"In high-density DRAM'S, a large peak current of typically 200-300mA occurs when sense amplifiers start latching in a conventional scheme (Figure la), resulting in intolerable power bus noise. Four-phase drive for PMOS restoring was reported to reduce the pe& current by triggering four pull-up transistors successively.[l] The initial sensing operation by NMOS latches, however, is more critical to signal margjn and sensing speed.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An on-chip smart memory for a data flow CPU 数据流CPU的片上智能内存
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037519
G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges
{"title":"An on-chip smart memory for a data flow CPU","authors":"G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges","doi":"10.1109/VLSIC.1989.1037519","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037519","url":null,"abstract":"Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131836198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low power time-multiplexed SC speech spectrum analyzer 低功耗时复用SC语音频谱分析仪
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037504
J. Chang, Y. Tong
{"title":"A low power time-multiplexed SC speech spectrum analyzer","authors":"J. Chang, Y. Tong","doi":"10.1109/VLSIC.1989.1037504","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037504","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133581653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A modularized speech recognition processor LSI with a highly parallel structure 一种高度并行结构的模块化语音识别处理器LSI
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037516
J. Takahashi, S. Hamaguchi, K. Tansho, T. Kimura
{"title":"A modularized speech recognition processor LSI with a highly parallel structure","authors":"J. Takahashi, S. Hamaguchi, K. Tansho, T. Kimura","doi":"10.1109/VLSIC.1989.1037516","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037516","url":null,"abstract":"To aclualize a continuous speech recognition System with a large vocabulary, we proposed ring-my-pmessor architecture 11-21, This architecture has the two features: highly parallel DTW(Dynamie Time Warping) processing [31 capability. which is the main algorithm used to realim speech recognition. and array size flexibility. which makes it possible to determine the number of PE(hxessing Element) contained by the array processor according to vocabulwy si?.. This paper describes the PE-LSl’s architecture used to realize a high performance array processor and the VLSI implementation methodology. and discusses obtained resulu.","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-poswer wide-band amplifier using a new parasitic capacitance compensation technique 一种采用寄生电容补偿技术的低功耗宽带放大器
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037502
T. Wakimoto, Y. Akazawa
{"title":"A low-poswer wide-band amplifier using a new parasitic capacitance compensation technique","authors":"T. Wakimoto, Y. Akazawa","doi":"10.1109/VLSIC.1989.1037502","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037502","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124487875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range 一种类似锁存器的高密度cmos动态RAM失效机制——工作Vcc范围内的磁滞
Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI: 10.1109/VLSIC.1989.1037475
T. Furuyama, H. Ishiuchi, H. Tanaka, Y. Watanabe, Y. Kohyama, T. Kiroura, K. Muraoka, S. Sugiura, K. Natori
{"title":"A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range","authors":"T. Furuyama, H. Ishiuchi, H. Tanaka, Y. Watanabe, Y. Kohyama, T. Kiroura, K. Muraoka, S. Sugiura, K. Natori","doi":"10.1109/VLSIC.1989.1037475","DOIUrl":"https://doi.org/10.1109/VLSIC.1989.1037475","url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122254966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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