An on-chip smart memory for a data flow CPU

Abstract

Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.