2016 17th Latin-American Test Symposium (LATS)最新文献

Infrastructure for formal and dynamic verification of peripheral programming model 外围规划模型形式化和动态验证的基础设施

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-06-02 DOI: 10.1109/LATW.2016.7483364

W. S. Encinas, Francisco Araújo, H. Abrahim

{"title":"Infrastructure for formal and dynamic verification of peripheral programming model","authors":"W. S. Encinas, Francisco Araújo, H. Abrahim","doi":"10.1109/LATW.2016.7483364","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483364","url":null,"abstract":"Programming model is the abstraction of the operation of a digital peripheral, defining how the masters of the peripheral bus(es) (system processors, DMA engines, etc.) control and supervise the peripheral. It is typically implemented as a bank of registers, mapped into the bus address space and composed of bit-fields with distinct access policies. Due to its relevance and universality, a solution to automate the functional verification of its implementation is described in this paper. It is a non-proprietary solution based on industry standards, comprising a library with key properties for register banks and a method to automatically instantiate these properties for a particular peripheral, according to a register bank description database. This infrastructure is intended to be used both in static (exhaustive) and dynamic functional verification and not to be limited to functional verification of register banks. Examples on how to leverage this infrastructure for formal and simulation-based verification of other peripheral functionalities are presented. The conclusion describes our experiences using this solution, its limitations and future work.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transforming nanodevices into nanosystems: The N3XT 1,000X 将纳米器件转化为纳米系统:n3xt1000x

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483329

S. Mitra

{"title":"Transforming nanodevices into nanosystems: The N3XT 1,000X","authors":"S. Mitra","doi":"10.1109/LATW.2016.7483329","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483329","url":null,"abstract":"Summary form only given. The computing demands of future abundant-data applications far exceed the capabilities of today's electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency. However, emerging nanomaterials and nanodevices face major obstacles such as inherent imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible. The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) transistors using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency, (b) high-density nonvolatile resistive and magnetic memories, (c) Ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory for fine-grained connectivity, (d) new architectures for computation immersed in memory, and (e) new materials technologies and their integration for efficient heat removal. N3XT hardware prototypes represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual nanosystems. Compared to conventional approaches, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude, thereby enabling new frontiers of applications for both mobile devices and the cloud.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129179536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fault simulation in radiation-hardened SOI CMOS VLSIs using universal compact MOSFET model 基于通用紧凑MOSFET模型的抗辐射SOI CMOS vlsi故障仿真

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483350

K. Petrosyants, L. Sambursky, I. Kharitonov, B. Lvov

引用次数: 5

A HW-dependent software model for cross-layer fault analysis in embedded systems 基于hw的嵌入式系统跨层故障分析软件模型

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483356

C. Bartsch, Nico Rödel, Carlos Villarraga, D. Stoffel, W. Kunz

{"title":"A HW-dependent software model for cross-layer fault analysis in embedded systems","authors":"C. Bartsch, Nico Rödel, Carlos Villarraga, D. Stoffel, W. Kunz","doi":"10.1109/LATW.2016.7483356","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483356","url":null,"abstract":"With the advent of new microelectronic fabrication technologies new hardware devices are emerging which suffer from an intrinsically higher susceptibility to faults than previous devices. This leads to a substantially lower degree of reliability and demands further improvements of error detection methods. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. Instead, an application-dependent approach should be taken, i.e., strategies for test and error resilience must target only those errors that can actually have an effect in the situations in which the hardware is being used. In this paper, we propose a method to inject faults into hardware and to formally analyze their effects on the software behavior. We describe how this analysis can be implemented based on a recently proposed hardware-dependent software model called program netlist. We show how program netlists can be extended to formally model the behavior of a program in the event of one or more hardware faults. First experimental results are presented to demonstrate the feasibility of our approach.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130796585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Analyzing NBTI impact on SRAMs with resistive-open defects 分析NBTI对具有阻性开口缺陷的sram的影响

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483345

M. Martins, G. Medeiros, T. Copetti, F. Vargas, L. Bolzani

引用次数: 7

A deep analysis of SEU consequences in the internal memory of LEON3 processor 对LEON3处理器内存中SEU后果的深入分析

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483358

Afef Kchaou, W. H. Youssef, R. Tourki, F. Bouesse, P. Ramos, R. Velazco

引用次数: 3

Single Trojan injection model generation and detection 单木马注入模型生成和检测

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483361

Harini Bhamidipati, D. Saab, J. Abraham

引用次数: 1

On automatic software-based self-test program generation based on high-level decision diagrams 基于高级决策图的自动软件自测程序生成

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483357

Artjom Jasnetski, R. Ubar, A. Tsertov

引用次数: 7

Using traffic monitoring to tolerate multiple faults in 3D NoCs 利用流量监控容忍3D noc中的多个故障

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483341

A. Kologeski, H. C. Zanuz, F. Kastensmidt

{"title":"Using traffic monitoring to tolerate multiple faults in 3D NoCs","authors":"A. Kologeski, H. C. Zanuz, F. Kastensmidt","doi":"10.1109/LATW.2016.7483341","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483341","url":null,"abstract":"The main reason to invest in 3D circuits adoption is the possibility of decrease the wire length, replacing horizontal wires by shorter vertical through-silicon-vias (called of TSVs). As a consequence, a better performance is expected and other optimizations also can be obtained in comparison with planar technology. In relation to 3D circuits, the networks-on-chip (NoCs) receiving special attention because they are very used to provide efficient communication with wide parallelism. However, the development of 3D circuits is not trivial, being very common appear imperfections and manufacture problems, mainly in sensitive regions as the TSVs. Thus, the main contribution of this work is to allow the usability of the NoC in 3D circuits even in the presence of multiple defective TSVs, with minimal impact on the latency results. In this way, the behavior of the routing algorithm called Elevator-First, to tolerate defective TSVs, will be analyzed. In order to provide an appropriated alternative path to forward the traffic flow in the presence of multiple faulty TSVs, the use of traffic flow monitors has been proposed. The results obtained for the considered scenarios of simulation prove that the strategy can be very efficient, shown that is possible to improve more than 50% of latency in relation to the original algorithm evaluated without traffic flow analysis.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122833962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance evaluation of radiation hardened analog circuits based on Enclosed Layout geometry 基于封闭布局几何的抗辐射模拟电路性能评价

2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483351

G. Cardoso, T. Balen

{"title":"Performance evaluation of radiation hardened analog circuits based on Enclosed Layout geometry","authors":"G. Cardoso, T. Balen","doi":"10.1109/LATW.2016.7483351","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483351","url":null,"abstract":"This paper presents an investigation on the performance impacts of employing Enclosed Layout Transistor (ELT) to the design of analog building blocks. A common-source (CS) amplifier is considered as case study, to which this layout technique is applied. SPICE simulations are performed, considering two different methodologies to estimate the effective aspect ratio (W/L) of the ELT devices. The extracted equivalent W/L using a commercial design tool is compared with a well-known mathematical model presented in the literature. The simulations were carried out considering three different channel lengths for the CS amplifier. The possibility of setting the transistor drain as the inner or outer terminal of the ELT was also investigated. According to the obtained results, considering a 0.18μm technology, there may be significant performance differences, both in the DC and AC behavior of the amplifier. Additionally, in order to improve the achievable aspect ratio range of square ELTs, we propose to use parallel and series associations of enclosed devices. Depending on the desired W/L, it is also possible to save silicon area with such associations.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130165046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7