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2016 17th Latin-American Test Symposium (LATS)最新文献

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A probabilistic model for stuck-on faults in combinational logic gates 组合逻辑门卡死故障的概率模型
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483337
Rafael B. Schivittz, D. Franco, C. Meinhardt, P. Butzen
{"title":"A probabilistic model for stuck-on faults in combinational logic gates","authors":"Rafael B. Schivittz, D. Franco, C. Meinhardt, P. Butzen","doi":"10.1109/LATW.2016.7483337","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483337","url":null,"abstract":"Reliability in advanced CMOS devices is a critical issue that can supersede the benefits of technology shrinking process. The Probabilistic Transfer Matrix (PTM) is the basis of more common reliability evaluation models. This work presents a probabilistic model for stuck-on faults in combinational logic gates, considering the individual fault probability of each logic function input vector. It shows that considering the same fault probability for all input vectors underestimates the input influence on the gate reliability. These probabilities can be used as inputs in PTM models to provide results that are more accurate and increase the circuit reliability.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122338933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Soft error analysis in embedded software developed with & without operating system 有/无操作系统嵌入式软件的软误差分析
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483355
L. Casagrande, F. Kastensmidt
{"title":"Soft error analysis in embedded software developed with & without operating system","authors":"L. Casagrande, F. Kastensmidt","doi":"10.1109/LATW.2016.7483355","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483355","url":null,"abstract":"This work presents a comparative analysis of soft error susceptibility in a well-known embedded microprocessor ARM Cortex-A9 single core, widely used along with safety critical applications, running embedded software developed for a bare metal environment and with operating system. The soft error analysis is performed by fault injection on OVPSim-FIM simulator platform. The faults injection campaign injects thousands of bit-flips in the microprocessor register file while executing a set of benchmarks with a diverse code behavior from control flow dependence to data intensive. Results present the percentage of masking faults, the classification of the errors and the number of exceptions detected by the operating system. The proposed method and the obtained results can help guiding software developers in choosing different architectures of the code in order to improve fault masking.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"420 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126708944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dependable on-chip infrastructure for dependable MPSOCs 可靠的片上基础设施，可靠的mpsoc
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483366
M. Kochte, H. Wunderlich
{"title":"Dependable on-chip infrastructure for dependable MPSOCs","authors":"M. Kochte, H. Wunderlich","doi":"10.1109/LATW.2016.7483366","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483366","url":null,"abstract":"Today's MPSOCs employ complex on-chip infrastructure and instrumentation for efficient test, debug, diagnosis, and post-silicon validation, reliability management and maintenance in the field, or monitoring and calibration during operation. To enable flexible and efficient access to such instrumentation, reconfigurable scan networks (RSNs) as recently standardized by IEEE Std 1687 can be used. Given the importance of infrastructure for the dependability of the whole MPSOC, however, the RSN itself must be highly dependable. This paper addresses dependability issues of RSNs including verification, test, and security, and their importance for dependable MPSOCs. First research results are summarized, and open questions for future work are highlighted.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116845695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design 有效评估组合细胞库设计的基准生成方法的硅上验证
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483353
M. D. Carvalho, Maurício Altieri, L. Puricelli, Renato P. Butzen, R. Ribas, E. Fabris
{"title":"On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design","authors":"M. D. Carvalho, Maurício Altieri, L. Puricelli, Renato P. Butzen, R. Ribas, E. Fabris","doi":"10.1109/LATW.2016.7483353","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483353","url":null,"abstract":"This work presents the validation in silicon of a test chip for the evaluation of ensembles of combinational CMOS gates (cell library). The design methodology and the architecture of this simple, efficient and easy-to-use test circuit were already proposed theoretically in the past, having been demonstrated its functionality only through partial electrical simulations. The fabrication and measurements over on-silicon prototype provide important information about design improvement possibilities of such a test circuit and its architecture. The results are presented and discussed in this paper.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115756978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hybrid soft error mitigation techniques for COTS processor-based systems 基于COTS处理器系统的混合软错误缓解技术
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483347
E. Chielle, B. Du, F. Kastensmidt, S. Cuenca-Asensi, L. Sterpone, M. Reorda
{"title":"Hybrid soft error mitigation techniques for COTS processor-based systems","authors":"E. Chielle, B. Du, F. Kastensmidt, S. Cuenca-Asensi, L. Sterpone, M. Reorda","doi":"10.1109/LATW.2016.7483347","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483347","url":null,"abstract":"In this paper we combine a set of software-based fault tolerance techniques with a hardware module that monitors the trace port, and explore from an experimental point of view the fault coverage against soft errors in COTS processors that can be achieved. The costs in terms of performance and memory are also evaluated. Fault injection results show fault coverage is superior to the state-of-the-art techniques with lower performance and memory overheads.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116618766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-core ARM Cortex-A9双核串行和并行应用的软误差分析
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483359
G. Rodrigues, F. Kastensmidt
{"title":"Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-core","authors":"G. Rodrigues, F. Kastensmidt","doi":"10.1109/LATW.2016.7483359","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483359","url":null,"abstract":"This work presents an analysis of the occurrence of software errors at ARM Cortex-A9 dual-core processor. Fault injection results compare the error rate and their causes. Results show that different parallelization algorithms can have different error rates, and that there is a tendency on parallel applications to have more silent data corruption errors than their sequential counterparts.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130815443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Checksum based error detection in linearized representations of non linear control systems 非线性控制系统线性化表示中基于校验和的错误检测
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483362
Suvadeep Banerjee, A. Chatterjee, J. Abraham
{"title":"Checksum based error detection in linearized representations of non linear control systems","authors":"Suvadeep Banerjee, A. Chatterjee, J. Abraham","doi":"10.1109/LATW.2016.7483362","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483362","url":null,"abstract":"While the past decades have seen major revolutions in the computing and communication industries, the next decade will experience a proliferation of intelligent autonomous systems capable of performing complex tasks. These systems will consist of a plethora of sensors communicating with each other to achieve specified system level objectives. The success and deployment of these systems in commercial arena depends on the reliability and security of the system design. In this work, we discuss error detection methodologies that can detect sensor failures and actuator malfunctions in a linearized representation of a non-linear control system. We demonstrate the proposed approaches on the linearized representation of the classical non-linear problem of an inverted pendulum which has a linear Kalman filter as its sensor and a linear servo motor as its actuator. Simulation results show the effectiveness of the proposed methodology.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126948835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluating the effects of single event upsets in soft-core GPGPUs 评估单事件干扰对软核gpgpu的影响
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483346
Werner Nedel, F. Kastensmidt, J. Azambuja
{"title":"Evaluating the effects of single event upsets in soft-core GPGPUs","authors":"Werner Nedel, F. Kastensmidt, J. Azambuja","doi":"10.1109/LATW.2016.7483346","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483346","url":null,"abstract":"Graphic Processing Units have become popular in a broad range of applications due to their high computational power and low prices. Among the applications there are the safety critical ones, where fault tolerance is mandatory. This paper presents a fault injection methodology to evaluate a soft-core General Purpose GPU design over Single Event Upsets in its register files. Different configurations of CUDA algorithms are explored to verify their impact on the GPU's behavior during a fault injection campaign. This paper also presents an error characterization analysis by verifying the GPUs memories and program counters in order to evaluate the real impact of the fault in the GPU, even if the fault does not result in an error in the final output of the system. Results can help designers developing fault tolerant techniques in an effective fashion.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"41 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125882097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Radiation effects in low power and ultra low power voltage references 低功率和超低功率电压参考中的辐射效应
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1166/jolpe.2016.1453
Daniel Fusco, T. Balen
{"title":"Radiation effects in low power and ultra low power voltage references","authors":"Daniel Fusco, T. Balen","doi":"10.1166/jolpe.2016.1453","DOIUrl":"https://doi.org/10.1166/jolpe.2016.1453","url":null,"abstract":"This work investigates the effects of ionizing radiation in low power and ultra-low power voltage references. Two specific circuits were selected as case studies, both designed in IBM 130nm technology. By means of SPICE simulation, the electrical equivalent effects of Total Ionizing Dose (TID) were simulated, corresponding to a total dose of 500krad. A worst case simulation of Single Event Transients (SET) was also performed. Results indicate a better behavior under radiation (TID) for low power voltage references than the observed for the ultra-low power counterpart. The temperature of operation affects the ultra-low power circuits changing the circuit response for the simulated SETs, while for low power circuits the results are not affected. The particularities of low power circuit that make them vulnerable to radiation effects are pointed out and possible mitigation strategies are discussed.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reliability analysis of majority voters under permanent faults 永久性故障下多数选民的可靠性分析
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483360
Eduardo Liebl, C. Meinhardt, P. Butzen
{"title":"Reliability analysis of majority voters under permanent faults","authors":"Eduardo Liebl, C. Meinhardt, P. Butzen","doi":"10.1109/LATW.2016.7483360","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483360","url":null,"abstract":"CMOS systems have become more susceptible to permanent and transient faults due to the technology scaling. Triple Modular Redundancy is a widely used technique for fault-tolerance. The weak point of this technique is the majority voter. Many researches propose different implementations of voter circuits to tolerate transient faults, but they usually do not evaluate permanent faults. This work investigates the robustness of different majority voters under stuck-on and stuck-open faults. The results show a difference up to 5X in the capacity of tolerate permanent faults.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122374828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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