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System-level diagnosis for WSN: A heuristic WSN系统级诊断:一种启发式方法
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483365
Mauricio de Oliveira Barros, Andréa Weber
{"title":"System-level diagnosis for WSN: A heuristic","authors":"Mauricio de Oliveira Barros, Andréa Weber","doi":"10.1109/LATW.2016.7483365","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483365","url":null,"abstract":"Wireless Sensor Networks are distinguished by two main characteristics: they are both prone to failures, mainly those encharged of ambiental monitoring, and aware of energy consumption. We propose to address these challenges by means of a fault tolerant approach, known as system-level diagnosis. In this approach, a subset of the sensors in a network is asked to perform mutual tests among themselves in order to achieve diagnosis, more specifically, to know which t sensors in a set of n, where n ≥ 2t + 1 are in a faulty state. The set of tests to be performed by the sensors involved in diagnosis is a connection assignment. An optimal connection assignment has n = 2t +1 nodes. In previous works, it has been proven that the Optimal Design Testing Assignment, ODTA approach, is optimal under the assumptions of diagnosability of a system. Nevertheless, in order to achieve optimality in terms of minimum energy consumption, the sensors that take part into diagnosis must be choosen from the vicinity of the sensors under suspicion, which is a problem supposed to be computationally intractable. We present an heuristic to address this challenge and compare it with the optimal solution obtained through linear programming.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The hype, myths, and realities of testing 2.5D/3D integrated circuits 测试2.5D/3D集成电路的炒作、神话和现实
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483326
K. Chakrabarty
{"title":"The hype, myths, and realities of testing 2.5D/3D integrated circuits","authors":"K. Chakrabarty","doi":"10.1109/LATW.2016.7483326","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483326","url":null,"abstract":"Summary form only given. Despite the numerous benefits offered by 2.5D/3D integration, testing remains a major obstacle that hinders its widespread adoption. Concerns related to test cost, yield and reliability continue to derail the commercial exploitation of 2.5D/3D ICs. Test techniques and design-for-testability (DfT) solutions are now being explored in the research community, with considerable focus on wafer probing, pre-bond test of passive interposers, test access to modules in stacked dies, cost modeling, and the targeting of new defect types. In this talk, the speaker will examine the hype, myths, and realities of 2.5D/3D ICs. He will reflect on some of the over-hyped claims and expose the many myths that have been exposed in recent years. He will present a reality-check on testing and DfT challenges, and describe some of the recent solutions being advocated for these challenges. The key questions to be addressed are: \"What to Test? How to Test? When to Test?\" To answer these questions, the presentation will cover pre-bond testing of TSVs and interposers, DfT solutions and optimization for stack testing, and test-flow selection.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121441845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs 基于IEEE1687的复杂soc故障管理系统的在线故障分类与处理
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483342
K. Shibin, S. Devadze, A. Jutman
{"title":"On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs","authors":"K. Shibin, S. Devadze, A. Jutman","doi":"10.1109/LATW.2016.7483342","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483342","url":null,"abstract":"Semiconductor products manufactured with latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming even more expensive and one cannot rely on them alone. In addition to mitigating/correcting the faults, the system may systematically monitor, detect, localize, diagnose and classify them (manage faults). As a result of such fault management approach, the system may continue operating and degrade gracefully even in case if some of the system's resources become unusable due to intolerable faults. This works proposes a fault classification and handling methodology that fits to an event-driven on-line fault monitoring, signaling and management architecture based on IEEE1687 IJTAG and suitable for a modern complex SoC with many heterogeneous cores.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127290353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Proposal of a functional safety methodology applied to fault tolerance in FPGA applications 提出了一种用于FPGA容错的功能安全方法
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483331
B. Flesch, Bianca S. Brand, R. M. Figueiredo, L. R. Prade, M. R. D. Silva
{"title":"Proposal of a functional safety methodology applied to fault tolerance in FPGA applications","authors":"B. Flesch, Bianca S. Brand, R. M. Figueiredo, L. R. Prade, M. R. D. Silva","doi":"10.1109/LATW.2016.7483331","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483331","url":null,"abstract":"This paper proposes a functional safety methodology applied to fault tolerance in FPGA applications by evaluating a case study in digital signal processing (DSP) field. This study is based on the safety standard IEC 61508 that states a safe system must be capable of detecting faults and it should have a safety mode. So, functional evaluations of a configurable DSP module were needed to define this methodological proposal. Besides, identification of its critical paths and proper definition of safety architectures were done. The case study was developed in configurable hardware. Furthermore, due to the influences of external factors, such as temperature, electromagnetic fields, among others, together with the advance of technology that reduces the components' size, entails in a much bigger occurrence of faults in a circuit. Hence, preliminary results from the use of this methodology indicated a reduction of up to 95 % in Single Event Transients (SETs) occurrence as well as a hardware area increase from 60 % to 163 %.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129140416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A control path aware metric for grading functional test vectors 用于分级功能测试向量的控制路径感知度量
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483339
K. Gent, M. Hsiao
{"title":"A control path aware metric for grading functional test vectors","authors":"K. Gent, M. Hsiao","doi":"10.1109/LATW.2016.7483339","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483339","url":null,"abstract":"Functional, at-speed test vectors play a critical role in targeting circuit defects not easily detected by traditional scan vectors. Fault simulating these vectors is generally computationally expensive since these tests are often applied at the system level without individual testing of modules within the hierarchy. As a result, fault grading techniques have become necessary to judge the quality of these test vectors. In this work, we propose a control path aware, rule-based statement coverage metric at the Register Transfer Level (RTL) to capture faulty behavior of statements along distinct operation paths within the circuit description. Experiments show that our metric has a strong correlation with gate level defect models across a variety of benchmarks, including the microprocessor or 1200 with a power management unit. Additionally, the metric shows high levels of scalability, providing up to two orders of magnitude reduction in execution time compared to fault simulation and up to an order of magnitude improvement over logic simulation based fault grading techniques.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fault model qualification by assertion mining 基于断言挖掘的故障模型鉴定
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483338
Alessandro Danese, J. Mocci, G. Pravadelli
{"title":"Fault model qualification by assertion mining","authors":"Alessandro Danese, J. Mocci, G. Pravadelli","doi":"10.1109/LATW.2016.7483338","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483338","url":null,"abstract":"The process of measuring the quality of a fault model is a key ingredient for implementing effective verification/testing phases based on fault injection. Most of the existing approaches for the qualification of a fault model base their evaluation on the comparison of the achieved fault coverage against other code coverage metrics, or against the fault coverage achieved by different fault models, sometimes at the varying of the abstraction level. However, these approaches do not explicitly provide a measure of the accuracy of the fault injection with respect to the actual functional behaviours implemented in the design under verification/testing (DUV/T). Thus, the achievement of 100% fault coverage does not necessarily imply that all the design's behaviours have been accurately perturbed by the selected fault model. To provide a more accurate evaluation of fault models, this paper proposes a methodology based on assertion mining, i.e., automatic extraction of temporal assertions from the simulation of the DUV/T. Mined assertions are then used to highlight behaviours of the DUV/T that are not accurately perturbed by the selected fault model.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114009465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage 采用双电源电压降低功耗的NBTI电路可靠性方法
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483344
Freddy Forero, Andres F. Gomez, V. Champac
{"title":"A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage","authors":"Freddy Forero, Andres F. Gomez, V. Champac","doi":"10.1109/LATW.2016.7483344","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483344","url":null,"abstract":"Actually there is a great interest of new methodologies for reducing the power consumption of integrated circuits. Power consumption raises the operating temperature that devices experience. Consequently, circuit reliability is affected due to temperature-dependent mechanisms like Negative Bias Temperature Instability (NBTI). This paper proposes a methodology based on dual supply voltage technique to mitigate delay degradation due to NBTI for applications requiring to reduce the power consumption. In the proposed methodology, the low voltage supply is slightly lower than the high (nominal) voltage supply. Therefore, voltage level converters are not required. A gate metric is proposed to estimate the benefit of lowering the supply voltage of a gate on circuit power consumption and delay degradation. The results show that NBTI-induced delay degradation and power consumption are reduced at some small delay penalty. This leads to circuits with lower power consumption and higher reliability.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128595093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A SystemC-based platform for assertion-based verification and mutation analysis in systems biology 系统生物学中基于断言的验证和突变分析的基于systemc的平台
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483363
Daniele Coati, Rosario Distefano, N. Bombieri, F. Fummi, M. Mirenda, C. Laudanna, R. Giugno
{"title":"A SystemC-based platform for assertion-based verification and mutation analysis in systems biology","authors":"Daniele Coati, Rosario Distefano, N. Bombieri, F. Fummi, M. Mirenda, C. Laudanna, R. Giugno","doi":"10.1109/LATW.2016.7483363","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483363","url":null,"abstract":"Boolean models are gaining an increasing interest for reproducing dynamic behaviours, understanding processes, and predicting emerging properties of cellular signalling networks through in-silico experiments. They are emerging as a valid alternative to the quantitative approaches (i.e., based on ordinary differential equations) for exploratory modelling when little is known about reaction kinetics or equilibrium constants in the context of gene expression or signalling. Even though several approaches and software have been recently proposed for logic modelling of biological systems, they are limited to specific modelling contexts and they lack of automation in analysing biological properties such as complex attractors, molecule vulnerability, dose response. This paper presents a design and verification platform based on SystemC that applies methodologies and tools well established in the electronic-design automation (EDA) field such as assertion-based verification (ABV) and mutation analysis, which allow complex attractors (i.e., protein oscillations) and robustness/sensitivity of the signalling networks to be simulated and analysed. The paper reports the results obtained by applying such verification techniques for the analysis of the intracellular signalling network controlling integrin activation mediating leukocyte recruitment from the blood into the tissues.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131012126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A layered approach for fault tolerant NoC-based MPSoCs — Special session: Dependable MPSoCs 基于noc的容错mpsoc的分层方法——特殊会话:可靠的mpsoc
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483367
E. Wächter, Francisco F. S. Barreto, Vinicius Fochi, Alexandre M. Amory, F. Moraes
{"title":"A layered approach for fault tolerant NoC-based MPSoCs — Special session: Dependable MPSoCs","authors":"E. Wächter, Francisco F. S. Barreto, Vinicius Fochi, Alexandre M. Amory, F. Moraes","doi":"10.1109/LATW.2016.7483367","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483367","url":null,"abstract":"Fault tolerant design has a key role in current nanometric technologies, leading to research on fault mitigation techniques for NoC-based MPSoCs. Most of the state-of-the-art papers present partial solutions to design a fault tolerant MPSoC, i.e., they present fault tolerant mechanisms for either NoCs or processing elements (PEs). The goal of this paper is to propose a comprehensive set of recovery mechanisms, organized in a layered stack, ensuring the correct execution of applications in the presence of transient or permanent faults, for both NoC and PEs. Faults injected into the NoC may induce it to operate in degraded mode or require the search of fault-free paths. In both cases, the communication is reestablished in less than 50 microseconds, using an end-to-end recovery mechanism. Faults injected into the PEs fire a lightweight and fast task relocation protocol, which executes in less than one millisecond.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128847122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications 三独立栅极晶体管:在数字、模拟和射频应用中的机会
2016 17th Latin-American Test Symposium (LATS) Pub Date : 2016-04-06 DOI: 10.1109/LATW.2016.7483368
P. Gaillardon, R. Magni, L. Amarù, M. Hasan, Ross M. Walker, B. S. Rodriguez, J. Christmann, E. Beigné
{"title":"Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications","authors":"P. Gaillardon, R. Magni, L. Amarù, M. Hasan, Ross M. Walker, B. S. Rodriguez, J. Christmann, E. Beigné","doi":"10.1109/LATW.2016.7483368","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483368","url":null,"abstract":"This paper provides a comprehensive review of Three-Independent-Gate Field-Effect Transistors (TIGFETs). In parallel to the focus on transistor scaling, an alternative approach to push further the performance of computing systems consists in increasing the functionalities of the basic transistors by means of additional gate controls. TIGFETs belong to this category of devices and can achieve different modes of operation according to the bias of the gate terminals. In particular, these devices are capable of (i) device-level polarity control, (ii) dynamic threshold modulation and (iii) subthreshold slope tuning down to ultra-steep-slope operation. The functionality increase at the device level leads to several design opportunities for digital, analog and RF applications.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124744339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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