On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design

Abstract

This work presents the validation in silicon of a test chip for the evaluation of ensembles of combinational CMOS gates (cell library). The design methodology and the architecture of this simple, efficient and easy-to-use test circuit were already proposed theoretically in the past, having been demonstrated its functionality only through partial electrical simulations. The fabrication and measurements over on-silicon prototype provide important information about design improvement possibilities of such a test circuit and its architecture. The results are presented and discussed in this paper.