Infrastructure for formal and dynamic verification of peripheral programming model

Abstract

Programming model is the abstraction of the operation of a digital peripheral, defining how the masters of the peripheral bus(es) (system processors, DMA engines, etc.) control and supervise the peripheral. It is typically implemented as a bank of registers, mapped into the bus address space and composed of bit-fields with distinct access policies. Due to its relevance and universality, a solution to automate the functional verification of its implementation is described in this paper. It is a non-proprietary solution based on industry standards, comprising a library with key properties for register banks and a method to automatically instantiate these properties for a particular peripheral, according to a register bank description database. This infrastructure is intended to be used both in static (exhaustive) and dynamic functional verification and not to be limited to functional verification of register banks. Examples on how to leverage this infrastructure for formal and simulation-based verification of other peripheral functionalities are presented. The conclusion describes our experiences using this solution, its limitations and future work.