Fault simulation in radiation-hardened SOI CMOS VLSIs using universal compact MOSFET model

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI CMOS ICs is presented. For this purpose, the universal compact SPICE SOI MOSFET model with account for TID, dose rate and single event effects is used. First, the model parameters extraction procedure is described in more details taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI MOS structures. The results of analog and digital SOI CMOS circuits simulation show the difference with experimental data not more than 10-20% for all types of radiation.