发布求助
文献互助 智能选刊 最新文献

The 3rd International IEEE-NEWCAS Conference, 2005.最新文献

筛选
英文 中文
Design and analysis of planar and lattice electrostatic comb drive actuators 平面和点阵静电梳状传动作动器的设计与分析
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496723
T. Kuendiger, G. M. Howard, P. Mokrian, M. Ahmadi, W. Miller
{"title":"Design and analysis of planar and lattice electrostatic comb drive actuators","authors":"T. Kuendiger, G. M. Howard, P. Mokrian, M. Ahmadi, W. Miller","doi":"10.1109/NEWCAS.2005.1496723","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496723","url":null,"abstract":"This paper presents an analysis of the electrostatic forces that act on a laterally driven comb drive actuator, in order to provide a clear understanding of the actuator geometry and its effects on system performance. Contrary to more familiar models, we provide a proper breakdown of the forces acting on a lateral comb drive structure by examining the electric field induced in a single actuator finger. Our results demonstrate the asymmetric nature of the forces, and its consequences. To counter these effects, we propose a novel actuator design which employs an out-of-plane interdigitated comb lattice. The simulation results comparing the new lattice design to the traditional planar comb drive actuator reveal a 66% increase in lateral actuation force, a 40% increase in change in capacitance per unit displacement, in addition to superior rectilinear stability under torsional forces.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134300616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integrated wide-band FSK demodulator based on ISPD PLL using a new model of an inverse sine function circuit 基于ISPD锁相环的集成宽带FSK解调器采用了一种新型的反正弦函数电路
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496745
M. Abdellaoui, B. Gassara, N. Masmoudi
{"title":"Integrated wide-band FSK demodulator based on ISPD PLL using a new model of an inverse sine function circuit","authors":"M. Abdellaoui, B. Gassara, N. Masmoudi","doi":"10.1109/NEWCAS.2005.1496745","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496745","url":null,"abstract":"The PLL ISPD is a new phase locked loop without using any filters, basis of an inverse sine phase detector (ISPD). In this paper, we proposed a new model of inverse sine function, more effective than the existing model in precision, simplicity, robustness. Besides, this model can be expressed to the order 1 or the order 3 according to the precision arranged by the foundry. The detail of the basic analysis and mathematical model of the ISPD PLL are presented and compared with the existing model. The digital design of the system involves the use of the SIMPLORER simulator for the hardware description language VHDL-AMS. We described the performance of an integrated wide-band FSK demodulator using the ISPD contrived to improve the characteristics of the system such as large bandwidth, high frequency, a wide keep range and seizure range, and a perfect reconstruction of an input signal.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130379068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Feasibility of a digital design flow of an asynchronous BCJR/MAP convolutional channel decoder 异步BCJR/MAP卷积信道解码器数字设计流程的可行性
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496735
K. Perta, K. Tepe
{"title":"Feasibility of a digital design flow of an asynchronous BCJR/MAP convolutional channel decoder","authors":"K. Perta, K. Tepe","doi":"10.1109/NEWCAS.2005.1496735","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496735","url":null,"abstract":"The current technology in the design of BCJR or MAP decoders utilizes standard electronic design and automation (EDA) tools in the synchronous paradigm. The BCJR/MAP decoder has gained large scale importance in convolutional coding, especially with its importance in turbo codes. This paper examines the feasibility and benefits of an asynchronous design of a BCJR/MAP decoder. A comparison against other gate level decoders is examined and promising results are shown.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of statistical clock skew variations on chip timing yield 统计时钟偏差变化对芯片时序良率的影响
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496752
K. R. Heloue, F. Najm
{"title":"Effect of statistical clock skew variations on chip timing yield","authors":"K. R. Heloue, F. Najm","doi":"10.1109/NEWCAS.2005.1496752","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496752","url":null,"abstract":"Integrated circuit design with sub-100nm technology requires closer attention to the effect of process variations on circuit timing. In a previous work, we had developed a method of statistical timing analysis in which the effect of process variations on circuit timing is assessed, given a generic logic path in a target design technology. In this work, we extend that previous work in an important way by incorporating into the analysis the effect of clock skew. The resulting model captures both die-to-die and within-die process variations, in both logic and clock paths, it handles within-die correlation using principal component analysis, and it leads to an expression for the resulting timing yield. Among other uses, this allows one to compute how much reduction one will see in the timing yield, for a given clock skew variance.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121117476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tunable microwave device: status and perspective 可调谐微波器件:现状与展望
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496728
E. Marsan, J. Gauthier, M. Chaker, K. Wu
{"title":"Tunable microwave device: status and perspective","authors":"E. Marsan, J. Gauthier, M. Chaker, K. Wu","doi":"10.1109/NEWCAS.2005.1496728","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496728","url":null,"abstract":"State-of-the-art frequency-agile technologies such as semiconductors, micro-electro-mechanical systems (MEMS) and ferrites are briefly overviewed and compared with the emerging ferroelectric techniques such as Ba/sub x/Sr/sub 1-x/TiO/sub 3/ (BST) that are becoming an attractive candidate for designing low-cost and miniaturized tunable integrated microwave devices such as filters and phase shifters. Particularities of ferroelectric materials are summarized and difficulties in connection with the use of BST thin-films in RF monolithic circuit design are addressed. On the basis of a commercially available sol-gel process, BST thin-films have successfully been deposited on alumina substrate to fabricate metal-insulator-metal (MIM) tunable capacitors. Early results of such capacitors at the room temperature indicate that a tunable ratio (C/sub max//C/sub min/) as high as 3.5 can be obtained over 1-6 GHz with 20 biasing voltage (34 V//spl mu/m) even though the ohmic loss remains high. This research also shows a 7% weak effect of hysteresis.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116011480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A low-voltage low-noise CMOS instrumentation amplifier for portable medical monitoring systems 一种用于便携式医疗监测系统的低压低噪声CMOS仪器放大器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496659
Honglei Wu, Y. Xu
{"title":"A low-voltage low-noise CMOS instrumentation amplifier for portable medical monitoring systems","authors":"Honglei Wu, Y. Xu","doi":"10.1109/NEWCAS.2005.1496659","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496659","url":null,"abstract":"This paper presents a low voltage low noise CMOS instrumentation amplifier (IA) suitable for portable health monitoring devices such as electrocardiogram (ECG) and electroencephalogram (EEG). Based on a current-mode topology, the IA is able to operate under a 1-V supply and consumes 50 /spl mu/W while providing a voltage gain of 150. An optimum trade-off between noise and voltage headroom is obtained by choosing appropriate operating points and sizes of transistors. The measured input referred noise integrated from 0.4Hz to 200Hz is 1.27 /spl mu/Vrms. The current-mode DC rejection circuit can suppress up to /spl plusmn/11 mV of input DC pedestal caused by medical electrodes, as well as the DC offset of the IA. The IA is fabricated in a standard 0.35/spl mu/m CMOS technology with a core chip area of 0.7mm/sup 2/.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Proportionate NLMS with orthogonal correction factors for stereophonic acoustic echo cancellation 具有正交校正因子的立体声回声消除比例NLMS
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496711
M. Borhani, V. Sedghi
{"title":"Proportionate NLMS with orthogonal correction factors for stereophonic acoustic echo cancellation","authors":"M. Borhani, V. Sedghi","doi":"10.1109/NEWCAS.2005.1496711","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496711","url":null,"abstract":"This paper presents an improved algorithm for stereophonic acoustic echo cancellation using proportionate normalized LMS algorithm with orthogonal correction factors (PNLMS-OCF). The convergence rate of improved algorithm and computational complexity are then analyzed.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115179719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Radio frequency CMOS integrated circuits for low power transceiver applications 用于低功率收发器的射频CMOS集成电路
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496721
R. Murji, M. Jamal Deen
{"title":"Radio frequency CMOS integrated circuits for low power transceiver applications","authors":"R. Murji, M. Jamal Deen","doi":"10.1109/NEWCAS.2005.1496721","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496721","url":null,"abstract":"In this paper we present design results related to integrated circuits for low power and high frequency transceiver implementations. We first consider the traditional LC voltage-controlled oscillator (VCO) and its operation. We then examine an implementation of a VCO that solves many practical problems with the traditional LC VCO implementation with the use of an automatic amplitude control (AAC) circuit. Finally, a method to extend the operating frequency of an oscillator using a wideband frequency doubler (FD) is discussed. The implemented VCO with AAC has an operating frequency of 7.2GHz, a tuning range of 410MHz, a phase noise of -108dBc/Hz@1MHz and it dissipates 4.32mW from a 1.8V supply. The implemented frequency doubler consumed 985/spl mu/W from a 1V supply and had a 3dB bandwidth of 4GHz.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power-constrained system-on-a-chip test scheduling using a genetic algorithm 基于遗传算法的功耗受限片上系统测试调度
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1142/S0218126606003106
H. Harmanani, Hassan A. Salamy
{"title":"Power-constrained system-on-a-chip test scheduling using a genetic algorithm","authors":"H. Harmanani, Hassan A. Salamy","doi":"10.1142/S0218126606003106","DOIUrl":"https://doi.org/10.1142/S0218126606003106","url":null,"abstract":"This paper presents a new and an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a SoC through efficient and compact test schedules. The problem is solved using a \"sessionless\" scheme that minimizes the number of idle test slots. The method can handle SoC test scheduling with and without power constraints. We present experimental results for various SoC examples that demonstrate the effectiveness of our method in short CPU time.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A low-power high-performance digital circuit for deep submicron technologies 用于深亚微米技术的低功耗高性能数字电路
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496684
G. Reza Chaji, S. M. Fakhraie
{"title":"A low-power high-performance digital circuit for deep submicron technologies","authors":"G. Reza Chaji, S. M. Fakhraie","doi":"10.1109/NEWCAS.2005.1496684","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496684","url":null,"abstract":"This paper presents a novel digital circuit design methodology that can support high-performance and low-power applications. In this method, reusing past internal voltages, signals are charged to Vdd/2 during the pre-charge cycle, so that the voltage of a signal is changed by just Vdd/2 during the evaluation cycle, resulting in a significant reduction in power consumption and propagation delay. The simulation results performed in 0.18/spl mu/m CMOS technology, demonstrate that the new circuit has three times improvement in terms of propagation delay in comparison to the equivalent domino dynamic logics. More importantly, its power consumption is 2.4 times less than that of the domino logics counterpart.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117176022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信