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A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications 用于低功率射频应用的1 mw 2 ghz q增强LC带通滤波器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-08-22 DOI: 10.1109/NEWCAS.2005.1496660
A. Naderi, M. Sawan, Y. Savaria
{"title":"A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications","authors":"A. Naderi, M. Sawan, Y. Savaria","doi":"10.1109/NEWCAS.2005.1496660","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496660","url":null,"abstract":"A low-power tunable LC bandpass filter is introduced for radio-frequencies applications. Center frequency of the filter can be tuned over a range of 144 MHz around 2 GHz at high quality factor (Q). Input signal is given to the LC resonator by an on-chip transformer, which reduces the power-consumption to 1 mW at a Q of 81. The Q-factor can also be tuned up to 150 when the center frequency remains at 2 GHz. Dynamic range of the filter is more than 50 dB with 1.2 V supply voltage. Modeling of the proposed filter and simulation results produced using IBM CMOS8RF 0.13 mum technology are presented","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132751491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An Integrated DVD_T Tuner 集成DVD_T调谐器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-22 DOI: 10.1109/NEWCAS.2005.1496720
F. Montaudon, D. Saias, A. Moutard, M. Bely, G. Provins, A. Dezzani, J. Roux, S. Dedieu, G. Wagner, E. Rouat, F. Bailleuil, P. Busson, E. André, F. Paillardet
{"title":"An Integrated DVD_T Tuner","authors":"F. Montaudon, D. Saias, A. Moutard, M. Bely, G. Provins, A. Dezzani, J. Roux, S. Dedieu, G. Wagner, E. Rouat, F. Bailleuil, P. Busson, E. André, F. Paillardet","doi":"10.1109/NEWCAS.2005.1496720","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496720","url":null,"abstract":"A fully CMOS integrated DVB_T RF analog tuner achieving a 6.5 dB noise figure is presented. The tuner is implemented in a 0.12 mum CMOS process and occupies a 16 mm2 area. The receiver is based on a double zero IF conversion and integrates within the receiver chain the frequency synthesizers and two 4 MHz bandwidth 14 bit analog digital converters. The VCO exhibits a -140 dBc phase noise at 1 MHz offset at 1.2 GHz","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133350936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On integrated CMOS-MEMS system-on-chip 集成CMOS-MEMS片上系统
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-22 DOI: 10.1109/NEWCAS.2005.1496726
S. Ghosh, M. Bayoumi
{"title":"On integrated CMOS-MEMS system-on-chip","authors":"S. Ghosh, M. Bayoumi","doi":"10.1109/NEWCAS.2005.1496726","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496726","url":null,"abstract":"The paper reviews the state-of-the-art in the field of CMOS-based microelectromechanical systems (MEMS). The different CMOS MEMS fabrication approaches, pre-CMOS, intermediate-CMOS, and post-CMOS, are summarized and examples are given.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124078061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An optimized systolic array architecture for full search block matching algorithm and its implementation on FPGA chips 全搜索块匹配算法的优化收缩阵列结构及其在FPGA芯片上的实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496700
M. Mohammadzadeh, M. Eshghi, M. Azadfar
{"title":"An optimized systolic array architecture for full search block matching algorithm and its implementation on FPGA chips","authors":"M. Mohammadzadeh, M. Eshghi, M. Azadfar","doi":"10.1109/NEWCAS.2005.1496700","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496700","url":null,"abstract":"In this paper, an optimized systolic array architecture for FSBMA is presented. This array architecture is implemented by RTL-level VHDL. It is synthesized for two FPGA families, Xilinx Spartan II and Xilinx Virtex II and the results for area occupation and maximum operating frequency are presented. The results show this array architecture is suitable for real-time video encoding systems with minimum hardware utilization and high performance.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127493241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A class of selective band-pass CNN linear filters 一类选择性带通CNN线性滤波器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496732
R. Matei
{"title":"A class of selective band-pass CNN linear filters","authors":"R. Matei","doi":"10.1109/NEWCAS.2005.1496732","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496732","url":null,"abstract":"In this paper we introduce a design method for a class of linear spatial filters implemented on CNNs. The aim is to realize selective band-pass filters with templates of minimum-size. The design procedure relies on 1D HR low-pass and band-pass prototype filters, from which we realize different types of 2D band-pass filters, basically belonging to two classes, namely filters with circular symmetry (based on a LP-BP transformation) and separable filters. Simulation results are provided which illustrate the capabilities of these filters on a real grayscale image.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116080615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimized distributed processing of scaling factor in CORDIC 优化了CORDIC中比例因子的分布式处理
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496664
G. Gilbert, D. Al-Khalili, C. Rozon
{"title":"Optimized distributed processing of scaling factor in CORDIC","authors":"G. Gilbert, D. Al-Khalili, C. Rozon","doi":"10.1109/NEWCAS.2005.1496664","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496664","url":null,"abstract":"CORDIC is a well known iterative algorithm used to evaluate various transcendental functions. There have been a number of papers describing various ways of speeding up this algorithm. One of the performance bottlenecks of CORDIC is the requirement to multiply the results of the x and y data path by a constant scaling factor. Depending on the architecture, such solutions might not necessarily provide added benefits. In this paper, processing of the scaling factor is applied in a distributed way in order to achieve maximum efficiency for both pipelined and recursive architectures.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122583904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high performance CABAC encoder 高性能CABAC编码器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496683
H. Shojania, S. Sudharsanan
{"title":"A high performance CABAC encoder","authors":"H. Shojania, S. Sudharsanan","doi":"10.1109/NEWCAS.2005.1496683","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496683","url":null,"abstract":"One key technique for improving the coding efficiency of H.264 video standard is the entropy coder, context-adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is far higher than the table driven entropy encoding schemes such as the Huffman coding. CABAC is also bit serial and its multi-bit parallelization is extremely difficult. For a high definition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, the authors provided efficient solutions for the arithmetic coder and the renormalizer. An FPGA implementation of the proposed scheme capable of 54 Mbps encoding rate and test results are presented. A 0.18 /spl mu/m ASIC synthesis and simulation shows 87 Mbps encoding rate utilizing an area of 0.42 mm/sup 2/.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128802386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Multipath greedy algorithm for canonical representation of numbers in the double base number system 双基数系统中数字规范化表示的多路径贪心算法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496665
G. Gilbert, J. Langlois
{"title":"Multipath greedy algorithm for canonical representation of numbers in the double base number system","authors":"G. Gilbert, J. Langlois","doi":"10.1109/NEWCAS.2005.1496665","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496665","url":null,"abstract":"The double base number system (DBNS) has been used in applications such as cryptography and digital filters. Two important properties of this type of representation are high redundancy and sparseness, which are key in eliminating carry propagation in basic arithmetic operations. High redundancy poses challenges in determining the canonical double base number representation (CDBNR) of an algebraic value. An exhaustive search for this representation can be computationally intensive, even for relatively small values. The greedy algorithm is very fast and simple to implement, but only allows for a single near canonical double base number representation (NCDBNR). The multipath greedy (MG) algorithm discussed in this paper is much faster than exhaustive search and gives better performance since it dramatically increases the likelihood of finding canonical representations. Since multiple starting points are used, this algorithm is able to find more than one NCDBNR in a single run.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124544993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On-chip analog floating-gate array programming in a submicron standard CMOS process using high voltage charge pumps 利用高压电荷泵实现亚微米标准CMOS工艺的片上模拟浮门阵列编程
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496714
M. Hooper, M. Kucic, P. Hasler
{"title":"On-chip analog floating-gate array programming in a submicron standard CMOS process using high voltage charge pumps","authors":"M. Hooper, M. Kucic, P. Hasler","doi":"10.1109/NEWCAS.2005.1496714","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496714","url":null,"abstract":"This paper presents a novel design of on-chip programming for floating-gate arrays in a 0.5 /spl mu/m standard CMOS N-well double poly process. Described in this paper is the complete design for integrating on chip the floating-gate programming infrastructure for programming a 10/spl times/10 array: electron injection and tunneling charge pumps, on-chip clock, and all interfacing circuitry to the array and pads. The three stage high voltage charge pump (HVCP) is utilized to modulate electron injection and six stage Schottky charge pumps (SCHCP) are utilized to modulate tunneling. Experimental results of hot-electron injection and electron tunneling for a floating-gate element are presented as well as simulation results for the critical interfacing circuitry and for the on-chip clock.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124615173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel hashing memories: an alternative to content addressable memories 并行散列存储器:内容寻址存储器的替代方案
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496691
P. Mahoney, Y. Savaria, G. Bois, P. Plante
{"title":"Parallel hashing memories: an alternative to content addressable memories","authors":"P. Mahoney, Y. Savaria, G. Bois, P. Plante","doi":"10.1109/NEWCAS.2005.1496691","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496691","url":null,"abstract":"Content addressable memories, or CAMs, are commonly used in applications requiring high speed access to data sets. This technology allows data items to be accessed in constant time based on content rather than on address. Unfortunately, this technology has several drawbacks: it occupies more die area per bit, costs more, dissipates more power, and has a higher latency. This article proposes an alternative to CAM technology based on a parallel hashing architecture. Simulations show that CAM performances can be matched and even surpassed while reducing cost and power consumption. The tradeoffs that exist between performance and cost are explored in the paper.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114710515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
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