发布求助
文献互助 智能选刊 最新文献

The 3rd International IEEE-NEWCAS Conference, 2005.最新文献

筛选
英文 中文
Analog ICs simulations using space charge waves in two-valley semiconductor films 双谷半导体薄膜中空间电荷波的模拟集成电路模拟
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496737
A. García-b., V. Grimalsky, E. Gutiérrez-D.
{"title":"Analog ICs simulations using space charge waves in two-valley semiconductor films","authors":"A. García-b., V. Grimalsky, E. Gutiérrez-D.","doi":"10.1109/NEWCAS.2005.1496737","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496737","url":null,"abstract":"Analog ICs simulations using space charge waves in two-valley semiconductor for microwave and millimeter range signal processing is presented. The formulation incorporates the full set of Maxwell's equations and the equations of motion of carriers based on a two-valley fully specified model providing a quantitative description of the space charge waves in thin-film n-GaAs. Numerical solutions to the system of equations indicate that the propagation and amplification of space charge waves in the thin film for four signals with different frequencies is possible. The present formulation can also find application where we need to know the interaction of electromagnetic waves and charge carriers.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126523016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multiplexer-based binary incrementer/decrementers 基于乘数器的二进制递增/递减数
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496662
Shaoqiang Bi, Wei Wang, A. Al-Khalili
{"title":"Multiplexer-based binary incrementer/decrementers","authors":"Shaoqiang Bi, Wei Wang, A. Al-Khalili","doi":"10.1109/NEWCAS.2005.1496662","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496662","url":null,"abstract":"In this paper, novel multiplexer (MUX)-based incrementer/decrementers are proposed. The proposed designs are more efficient in terms of speed and hardware complexity compared to the adder-based ones for both signed and unsigned cases. A FPGA implementation comparison shows that the proposed design reduces both area and delay close to 40%. The power consumed by the MUX-based design is almost 35% less than that of the carry propagation adder (CPA)-based design.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A fully reconfigurable controller dedicated to implantable recording devices 一个完全可重构的控制器，专用于植入式记录设备
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496671
J.-F. Roy, Mohamad Sawan
{"title":"A fully reconfigurable controller dedicated to implantable recording devices","authors":"J.-F. Roy, Mohamad Sawan","doi":"10.1109/NEWCAS.2005.1496671","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496671","url":null,"abstract":"Neural signals monitoring systems become a key issue to cortical bioelectrical comprehension research. This paper describes the implementation of a dynamically reconfigurable controller dedicated for real-time implantable acquisition systems. The authors presented the cortical signal's characteristics and the requirements needed to extract and reconstruct the signal once transmitted outside the implant. The implementation of a wavelet transformation used as a feature extraction for spike detection, compression and denoising techniques were reported. A packet based protocol permitted to communicate in both directions with the implant trough the wireless link. A complete 32 channels prototype based on an optimized pipelined architecture was implemented and the resources' usage for further expansion was discussed.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131546203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A low voltage CMOS bandgap reference 一个低电压CMOS带隙基准
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496749
Yeong-Tsair Lin, Wen-Yaw Chung, Dong-Shiuh Wu, Ho-Cheng Lin, R. Lin
{"title":"A low voltage CMOS bandgap reference","authors":"Yeong-Tsair Lin, Wen-Yaw Chung, Dong-Shiuh Wu, Ho-Cheng Lin, R. Lin","doi":"10.1109/NEWCAS.2005.1496749","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496749","url":null,"abstract":"In this paper, a low voltage bandgap reference (LVBR) is proposed and analyzed. An nMOS arrangement folded operational transconductance amplifier (OTA) is developed for the LVBR. From the Hspice simulation results, the proposed LVBR can be operated with sub-1V supply. The LVBR circuit, occupied an area of 0.12 mm/sup 2/, is design and fabricated in a doubly-poly quadruple-metal 0.35-/spl mu/m CMOS process. The circuit functions properly with minimum supply voltage of 0.88 V and consumes a power dissipation of 25 /spl mu/W. The circuit also provides a temperature coefficient of 20 ppm/K over a temperature range from -20 to 100/spl deg/C.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124556126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A hardware architecture for the generation of /spl omega/NAF random integers 用于生成/spl ω /NAF随机整数的硬件架构
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496750
L. Dupont, S. Roy, J. Chouinard
{"title":"A hardware architecture for the generation of /spl omega/NAF random integers","authors":"L. Dupont, S. Roy, J. Chouinard","doi":"10.1109/NEWCAS.2005.1496750","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496750","url":null,"abstract":"Width-/spl omega/ non-adjacent form (/spl omega/NAF) representation is commonly used in elliptic curve cryptography to speed up multiplication. However, conversion of an integer to its /spl omega/NAF representation can be quite costly, especially from a hardware point of view. This paper proposes a method to generate an integer directly in its /spl omega/NAF representation. A hardware implementation is also proposed.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123975232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Linearity enhancement in a configurable sigma-delta modulator 可配置σ - δ调制器的线性增强
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496663
A. Rusu, B. R. Jose, M. Ismail, H. Tenhunen
{"title":"Linearity enhancement in a configurable sigma-delta modulator","authors":"A. Rusu, B. R. Jose, M. Ismail, H. Tenhunen","doi":"10.1109/NEWCAS.2005.1496663","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496663","url":null,"abstract":"A highly linear sigma-delta modulator for dual-standard receivers is presented. The modulator makes use of low-distortion sigma-delta modulator architecture to attain high linearity over a wide bandwidth. The dual-band modulator employs a 2/sup nd/ order single-bit sigma-delta modulator with feedforward path for GSM mode and a 4/sup th/ order modified cascaded modulator with single-bit in the first stage and 4-bit in the second for WCDMA mode. The modulator is designed in TSMC 0.18/spl mu/m CMOS technology and operates at 1.8 supply voltage. It achieves in GSM/WCDMA mode a peak SNDR of 83/75dB, a 96/84dB SFDR and an IMD3 of -93/-82dB for an OSR of 160/16.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125807182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 3-10 GHz 0.13/spl mu/m CMOS body effect reuse LNA for UWB applications 3-10 GHz 0.13/spl mu/m CMOS体效应复用LNA用于超宽带应用
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496710
T. Taris, J. Bégueret, H. Lapuyade, Y. Deval
{"title":"A 3-10 GHz 0.13/spl mu/m CMOS body effect reuse LNA for UWB applications","authors":"T. Taris, J. Bégueret, H. Lapuyade, Y. Deval","doi":"10.1109/NEWCAS.2005.1496710","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496710","url":null,"abstract":"Focusing on low noise amplifier (LNA) which is one of the main building blocks in UWB receiver, this paper highlights the RF design constraints induced by the implementation of this key cell in a standard CMOS technology. An UWB input matching theory is proposed achieving a -13 dB S/sub 11/ from 2.8 to 10.5 GHz while the LNA is in a reuse implementation topology. Indeed this UWB LNA provides a 13 dB quasi-flat band gain from 2.8 to 12.8 GHz with a 4.2 dB average noise figure (NF). Operating under 1 V, this circuit addresses the low voltage constrain of modern CMOS technology whose the traditional cascade topology cannot to be compelled.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128369714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-power driving scheme for a-Si:H active-matrix organic light-emitting diode displays A - si:H有源矩阵有机发光二极管显示器的低功耗驱动方案
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496658
G. Reza Chaji, N. Safavian, A. Nathan
{"title":"A low-power driving scheme for a-Si:H active-matrix organic light-emitting diode displays","authors":"G. Reza Chaji, N. Safavian, A. Nathan","doi":"10.1109/NEWCAS.2005.1496658","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496658","url":null,"abstract":"This paper describes a low-power driving scheme along with a pixel circuit based on hydrogenated amorphous silicon (a-Si:H) technology for active matrix organic light emitting diode (AMOLED) displays. The driving scheme can provide different current levels for the OLED while compensating for long-term (and gradual) instabilities caused by material defect metastability which will make it amenable for use in AMOLED displays. Moreover, since the threshold voltage is known in this method, it can be used to compensate for the time-dependent errors of the charge injection and clock feed-through effects. Therefore, the error for a 3V shift in the VT of T1 is almost zero. More importantly, it has low power consumption because the line capacitance is charged just one time during the programming cycle. For example, the total power consumption of a QVGA array (240*320) is expected to be less than 1.5W.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"16 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123263796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 130nm partially depleted SOI technology menu for low-power applications 130nm部分耗尽SOI技术菜单，用于低功耗应用
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496670
N. L'Hostis, A. Valentian, A. Amara
{"title":"A 130nm partially depleted SOI technology menu for low-power applications","authors":"N. L'Hostis, A. Valentian, A. Amara","doi":"10.1109/NEWCAS.2005.1496670","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496670","url":null,"abstract":"In this paper, we present a technology-based menu where the target performance and power consumption are achieved by selecting a given design point (supply voltage, normal V/sub T/, low V/sub T/ and DTMOS transistors) according to a given application. Through analyses made at synthesis and silicon measurements levels, it is shown that the best results are obtained by optimizing the SOI technology for the targeted power supply voltage. At the nominal 1.2V supply voltage, this is achieved by setting a higher threshold voltage V/sub T/ to limit the cut-off currents. The power gains are in the order of 25% to 30% for the same performance. To further reduce the power dissipation, targeting the ultra-low-voltage range (0.5V) is very attractive when performance is not an issue. Using low-V/sub T/ SOI transistors allows significant gains in terms of speed and power. The power-delay product of a 16-bit multiplier is improved by a 2.4 factor.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122277021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A versatile memory-interface architecture for enhancing performance of video applications 用于增强视频应用程序性能的通用内存接口架构
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496748
M. Sinnathamby, N. Manjikian
{"title":"A versatile memory-interface architecture for enhancing performance of video applications","authors":"M. Sinnathamby, N. Manjikian","doi":"10.1109/NEWCAS.2005.1496748","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496748","url":null,"abstract":"This paper proposes a versatile memory-interface architecture that, through a mode switch, uses a two-dimensional array of DRAM banks for both general-purpose data storage and picture (or video) data storage. Additionally, in picture mode, the architecture supports both linear and block access of video pixel data. An efficient mapping scheme that maps video pixel data into the memory bank array to hide DRAM row activation latency is also proposed. The proposed memory-interface architecture is suitable for embedded memory in system-on-chip applications or for enhancement of commodity DRAM chips.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133196733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信