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A novel architecture of a re-configurable parallel DSP processor 一种新的可重构并行DSP处理器结构
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496709
P. Sinha, A. Sinha, D. Basu
{"title":"A novel architecture of a re-configurable parallel DSP processor","authors":"P. Sinha, A. Sinha, D. Basu","doi":"10.1109/NEWCAS.2005.1496709","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496709","url":null,"abstract":"High performance, flexibility and low power consumption are the most important issues in the current DSP architectures. While the fastest programmable DSP processors are unable to meet the speed requirements of many advanced signal/image processing applications, the ASICS are not always suitable because of their inflexibility. Recently, dynamically re-configurable FPGAs have emerged as high performance flexible programmable hardware to execute highly parallel, computationally intensive functions of image and signal processing applications. However, since the FPGAs are not optimised for any particular application, they can not offer highest possible performance at lowest silicon cost for a given signal processing application. This paper addresses these issues by introducing a novel re-conflgurable parallel DSP processor which eliminates the drawbacks of the FPGAs and ASICs and offers a balance between flexibility, reconfiguration latency and performance.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Scheduling of DSP algorithms onto heterogeneous multiprocessors with inter-processor communication 基于处理器间通信的异构多处理器上DSP算法的调度
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496751
A. Itradat, M. Ahmad, A. Shatnawi
{"title":"Scheduling of DSP algorithms onto heterogeneous multiprocessors with inter-processor communication","authors":"A. Itradat, M. Ahmad, A. Shatnawi","doi":"10.1109/NEWCAS.2005.1496751","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496751","url":null,"abstract":"In recent years a great deal of research has been conducted in the area of scheduling DSP data flow graphs (DFG) onto heterogeneous multiprocessing systems. However, there is not yet much research conducted for designing the scheduling algorithms that consider the inter-processor communication delays. This paper presents a novel technique to obtain time and processor schedules for cyclic DFGs representing DSP algorithms onto a heterogeneous multiprocessor systems by taking into consideration the inter-processor communication delays. In the proposed technique the communication delay between a pair of nodes of the different type is treated as a non-computing node, whereas that between a pair of nodes of the same type is taken into account by re-adjusting the firing times of the appropriate nodes of DFG. A simulation is carried to illustrate the proposed technique by applying it to a second-order digital filter. The results show the proposed technique can produce optimal time and processor-allocation schedules.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126848621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
High speed ADCs dedicated for wideband wireless receivers 高速adc专用于宽带无线接收机
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496729
M. Sawan, A. Djemouai, K. El-Sankary, H. Dang, A. Naderi, Y. Savaria, F. Gagnon
{"title":"High speed ADCs dedicated for wideband wireless receivers","authors":"M. Sawan, A. Djemouai, K. El-Sankary, H. Dang, A. Naderi, Y. Savaria, F. Gagnon","doi":"10.1109/NEWCAS.2005.1496729","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496729","url":null,"abstract":"In this paper the authors presented and discussed the design of different architectures of high-speed analog-to-digital converters (ADCs) dedicated for wideband wireless receivers such as software-defined radio systems. The interest of the authors concerns three different architectures: a pipelined 10-bit, 50 MS/s, a Flash 6-bit, 1-GS/s, and a band-pass sigma-delta 6-bit, 2-GS/s. A first version of the pipelined ADC and the Flash ADC was fabricated. As part of the sigma-delta ADC, a resonator operating at 2-GHz was fabricated. In addition to the design of these ADCs, a PCB card that supports these ADCs within a wireless receiver prototype was designed and tested. The ADCs technology of fabrication is the CMOS 0.18 /spl mu/m for the pipelined and the flash, and the CMOS 0.13 /spl mu/m for the band-pass sigma-delta.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124691248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An FPGA implementation of an OFDM adaptive modulation system OFDM自适应调制系统的FPGA实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496672
J. Veillcux, P. Fortier, S. Roy
{"title":"An FPGA implementation of an OFDM adaptive modulation system","authors":"J. Veillcux, P. Fortier, S. Roy","doi":"10.1109/NEWCAS.2005.1496672","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496672","url":null,"abstract":"This paper investigates the hardware and architecture requirements for an OFDM adaptive modulation system. The hardware modules for a baseband adaptive uncoded OFDM transmitter, receiver and feedback link have been implemented on an FPGA. This system is used for fast hardware-in-the-loop simulation when combined with the implementation of a wireless channel model. It is also demonstrated that one high-end FPGA chip can provide all the resources necessary for the implementation of the system.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Cartesian feedback feasibility study for a zero-IF WCDMA transmitter handset IC 零中频WCDMA发射机手持集成电路的笛卡尔反馈可行性研究
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496754
C. Tassin, P. Garcia, J.-P. Begueret, Y. Deval, D. Belot
{"title":"A Cartesian feedback feasibility study for a zero-IF WCDMA transmitter handset IC","authors":"C. Tassin, P. Garcia, J.-P. Begueret, Y. Deval, D. Belot","doi":"10.1109/NEWCAS.2005.1496754","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496754","url":null,"abstract":"A Cartesian feedback feasibility study is presented describing the main requirements of a WCDMA zero-IF transmitter IC. The transmitter architecture consists of an analog part with a forward modulator, a feedback demodulator and a digital part to adjust the phase rotation around the loop and to remove the DC offset and I/Q gain mismatches in the feedback path. Linearization performances are 27 dB ACPR improvement at 5 MHz offset and 15 dB ACPR improvement at 10 MHz.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132579330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reconfigurable receiver approach for 4G terminals and beyond 4G终端及以后的可重构接收器方法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496719
R. Kakerow, M. Mueller, D. Pienkowski, R. Circa, G. Boeck
{"title":"Reconfigurable receiver approach for 4G terminals and beyond","authors":"R. Kakerow, M. Mueller, D. Pienkowski, R. Circa, G. Boeck","doi":"10.1109/NEWCAS.2005.1496719","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496719","url":null,"abstract":"An overview on RF-front-end architectures and technologies for future reconfigurable mobile communication systems (4G-systems) is given. Favourable standard combinations are WCDMA and WLAN. RF front-end key components like low noise amplifiers, mixers, synthesizers and baseband variable gain amplifiers are treated, particularly with regard to reconfigurable systems.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"19 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132501978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A programmable DSP core for baseband processing 用于基带处理的可编程DSP核心
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496739
E. Tell, A. Nilsson, Dake Liu
{"title":"A programmable DSP core for baseband processing","authors":"E. Tell, A. Nilsson, Dake Liu","doi":"10.1109/NEWCAS.2005.1496739","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496739","url":null,"abstract":"A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors of complex data is used. Implementation of a demonstrator chip and firmware for wireless LAN applications has proven the instruction set to be very efficient, resulting in low program memory cost and moderate clock frequency requirements. The architecture also minimizes data memory size and accesses, which together with a high degree of hardware reuse results in very low silicon cost for multi-standard baseband processors.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An alternate approach to modular multiplication for finite fields [GF (2/sup m/)] using Itoh Tsujii algorithm 基于Itoh Tsujii算法的有限域模乘法的替代方法[GF (2/sup m/)]
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496668
S. Bharathwaj, K. Narasimhan
{"title":"An alternate approach to modular multiplication for finite fields [GF (2/sup m/)] using Itoh Tsujii algorithm","authors":"S. Bharathwaj, K. Narasimhan","doi":"10.1109/NEWCAS.2005.1496668","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496668","url":null,"abstract":"Modular arithmetic operations especially modular multiplication have extensive applications in elliptic curve cryptanalysis, error control coding and linear recurring sequences. These operations have steadily grown in the word size in the past. Current designs and approaches may not be the most efficient for such high word sizes. Also usually, most approaches optimize for either area or speed, not both. In this paper, we examine certain properties and elucidate certain alternative strategies of and on the Itoh Tsujii algorithm (Guajardo and Paar, 2002) that will make it suitable for this emerging scenario. These strategies take a holistic approach to the problem, and aims at optimizing both speed and area for a given word length. These claims are supported by mathematical analysis, simulation and synthesis of a prototype of the suggested strategy. We also examine various enhancements that can be effected in the given architecture.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Automatically retargetable pre-processor and assembler generation for ASIPs 自动重定位的预处理器和汇编程序生成的asp
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496756
L. Taglietti, J.O.C. Filho, D.C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos
{"title":"Automatically retargetable pre-processor and assembler generation for ASIPs","authors":"L. Taglietti, J.O.C. Filho, D.C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos","doi":"10.1109/NEWCAS.2005.1496756","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496756","url":null,"abstract":"During design space exploration, alternative CPUs are evaluated for an envisaged SoC, thereby requiring fast CPU models and efficient code generation tools. Candidate CPUs may be general-purpose processors, DSPs, micro-controllers or ASIPs. The ASIP is a particularly challenging alternative: since instruction-set architecture (ISA) tailoring is allowed, an ASIP cannot rely on pre-existent code generation tools. Each target ISA requires a new tool chain. Therefore, an automatically retargetable tool chain is mandatory. This paper focuses on a couple of tools from such a chain: pre-processor and assembler. It proposes robust and efficient techniques allowing retargetability through automatic tool generation from a given target ISA, which is formally described by architecture description language (ADL) constructs. Tool robustness results from formal techniques based on context-free grammars. Tool efficiency evidence is provided by experiments targeting three CPUs: MIPS, PowerPC 405 and PIC 16F84.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126170690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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