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The application of chaotic maps in image encryption 混沌映射在图像加密中的应用
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496703
Jiancheng Zou, Changzhen Xiong, Dongxu Qi, R. Ward
{"title":"The application of chaotic maps in image encryption","authors":"Jiancheng Zou, Changzhen Xiong, Dongxu Qi, R. Ward","doi":"10.1109/NEWCAS.2005.1496703","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496703","url":null,"abstract":"A new encryption algorithm based on chaotic map without transcendental knowledge of orbit distributing is proposed. The algorithm reduces iterative number and makes full use of chaotic property of map. The segmentation mechanism of 2D generalized baker transformation is used to enhance the key space and security of algorithm. The security analysis of the algorithm is given. The experiments show that the algorithm has the characteristic of sensitive to initial condition, high key space and pixel distributing uniformity.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121522903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A capacitor-free feed-forward compensated single-stage merged topology fully-differential CMOS folded cascode amplifier 一种无电容前馈补偿单级合并拓扑全差分CMOS折叠级联放大器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496697
S. Hasan, N. Ula
{"title":"A capacitor-free feed-forward compensated single-stage merged topology fully-differential CMOS folded cascode amplifier","authors":"S. Hasan, N. Ula","doi":"10.1109/NEWCAS.2005.1496697","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496697","url":null,"abstract":"This paper presents a capacitor-free feed-forward compensation technique for single-stage CMOS folded-cascode operational transconductance amplifiers (OTA) using a \"merged CMOS cascode transconductors\" topology. A phase margin of around 65 degrees can be achieved without the use of any \"added\" load capacitance for the open-loop amplifier. This ensures optimum step response (fast settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved \"fast sensing\" common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114542773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An alternative approach for generating linear-phase FIR filters from IIR-like filter blocks in cascade 从级联的类iir滤波器块生成线性相位FIR滤波器的另一种方法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496747
P. Arian, T. Saramaki, A. Fam
{"title":"An alternative approach for generating linear-phase FIR filters from IIR-like filter blocks in cascade","authors":"P. Arian, T. Saramaki, A. Fam","doi":"10.1109/NEWCAS.2005.1496747","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496747","url":null,"abstract":"The structure composed of a stable IIR filter G(z) in cascade with its anticausal counterpart G(z/sup -1/) is equivalent to a zero-phase IIR filter. Truncating the impulse responses of G(z) and G(z/sup -1/), followed by a subsequent delay transforms the structure into a linear-phase FIR. A design technique to implement the above scheme has already been proposed by the authors. This paper takes a new approach to the implementation problem by introducing a new truncation scheme, and illustrates its superiority for certain design specifications.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134064938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra-wideband (UWB) communications systems: an overview 超宽带(UWB)通信系统综述
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496688
T. Tsang, M. El-Gamal
{"title":"Ultra-wideband (UWB) communications systems: an overview","authors":"T. Tsang, M. El-Gamal","doi":"10.1109/NEWCAS.2005.1496688","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496688","url":null,"abstract":"This paper presents an overview of the ultra-wideband (UWB) technology for wireless communications systems. Following a brief review of the UWB basic principles, the characteristics of application specific UWB wireless systems are described. Design principles and challenges of UWB wireless systems, with an emphasis on monolithic implementations are discussed. Trade-offs between performance, power consumption, and technology choices are addressed. Examples of state-of-the-art UWB circuits and systems are presented.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132939840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
A systematic approach for design of broadband CMOS amplifiers 宽带CMOS放大器的系统设计方法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496675
K. Moez, M. Elmasry
{"title":"A systematic approach for design of broadband CMOS amplifiers","authors":"K. Moez, M. Elmasry","doi":"10.1109/NEWCAS.2005.1496675","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496675","url":null,"abstract":"This article presents a novel method for the design of broadband amplifiers in CMOS technology. The proposed design is based on equalizing the frequency response of NMOS transistors over the amplifier bandwidth. The compensating network is realized using passive elements available in CMOS technology. Simulation results indicate successful implementations of broadband amplifiers in 0.18 /spl mu/m CMOS with the bandwidth up to 30 GHz. The paper also reviews the design of broadband matching networks of the amplifier, completing the design process of broadband CMOS amplifiers.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132103868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compensation for within-die variations in dynamic logic by using body-bias 用体偏补偿动态逻辑中的模内变化
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496753
N. Azizi, Farid N. Najm
{"title":"Compensation for within-die variations in dynamic logic by using body-bias","authors":"N. Azizi, Farid N. Najm","doi":"10.1109/NEWCAS.2005.1496753","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496753","url":null,"abstract":"We propose a fine-grained scheme to compensate for within-die variations in dynamic logic to reduce the variation in leakage, delay and noise margin through body-biasing. We first show that the amount of body-bias compensation needed depends on the correlation that exists between gates, and then analytically show the possible reduction in the variance of the leakage of both a single and multiple dynamic logic gates. We then design a circuit to implement the system which provides the reduction in the variance of the leakage, delay and noise margin of dynamic logic gates and show that it produces a close match to the analytical results. In our design, the variance of a typical test circuit is reduced by 27% and the variance of the path delay is reduced by 33%.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116515711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Design and implementation of a reconfigurable architecture for (528, 518) Reed-Solomon codec IP (528,518) Reed-Solomon编解码器IP的可重构架构的设计与实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496743
Fu-Ke Chang, W. Hsu, Chien-Ching Lin, Hsie-Chia Chang
{"title":"Design and implementation of a reconfigurable architecture for (528, 518) Reed-Solomon codec IP","authors":"Fu-Ke Chang, W. Hsu, Chien-Ching Lin, Hsie-Chia Chang","doi":"10.1109/NEWCAS.2005.1496743","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496743","url":null,"abstract":"In this paper, an area-efficient Reed-Solomon (RS) codec IP with composite-field inverter is presented. For some specific applications such as flash memory controller using RS (528, 518) code over GF(2/sup 10/) to correct 4 errors, the RS decoder will stop receiving any new codeword until the on-going erroneous codeword to be corrected. It is that the circuit complexity can be reduced by sharing the registers and finite-field operation units. Moreover, the proposed hardware sharing architecture also includes the RS encoder. After implementing by 0.18/spl mu/m 1P6M standard cell slow library, the RS (528, 518) codec IP totally requires 2 finite-field multiplier, 1 composite-field inverter and 17(=4t+1) registers, where t is the number of correctable errors. In contrast with other architectures, at least 42% circuit complexity can be reduced in our proposal.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125295593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new wavelet-based method for despeckling SAR images 一种新的基于小波的SAR图像去噪方法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496736
M. Bhuiyan, M. Omair Ahmad, M. Swamy
{"title":"A new wavelet-based method for despeckling SAR images","authors":"M. Bhuiyan, M. Omair Ahmad, M. Swamy","doi":"10.1109/NEWCAS.2005.1496736","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496736","url":null,"abstract":"In this paper, a wavelet-based despeckling method is proposed for suppressing speckle noise in synthetic aperture radar (SAR) images. A new threshold is proposed to classify the wavelet coefficients into significant and insignificant ones. Local statistic in the wavelet domain is used to further classify the significant coefficients into the edge and non-edge coefficients. The edge coefficients remain unaltered, whereas the non-edge and the insignificant ones are reduced in magnitude. Experiments are carried out on a noise-free image corrupted with simulated speckle noise, and a real SAR image. The results show that the proposed method provides a performance better than that of other methods in terms of the peak signal-to-noise ratio and ability to suppress speckle in the homogeneous areas. In addition, it introduces a bias that is much smaller than that of the other methods as well as preserves edges quite well.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115581891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Area-efficient advanced multiuser WCDMA receiver 区域高效的先进多用户WCDMA接收机
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496731
S. Jomphe, K. Cheikhrouhou, J. Belzile, S. Affes, J. Thibault
{"title":"Area-efficient advanced multiuser WCDMA receiver","authors":"S. Jomphe, K. Cheikhrouhou, J. Belzile, S. Affes, J. Thibault","doi":"10.1109/NEWCAS.2005.1496731","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496731","url":null,"abstract":"The authors explored the benefits of employing STAR as a wideband CDMA receiver. It is shown that it inherently addresses data recovery and channel characterization through its analysis/synthesis paradigm. Simulation results carried out on real-world channel measurements showing the robustness and quick adaptation rate of STAR in terms of time-delay tracking performance and carrier frequency offset recovery were presented. Then an overview of the preferred hardware embodiment along with hard values in terms of hardware resource utilization, showing that a 24-user STAR-enabled 3G base station receivers can be realized within a single XC2V6000 FPGA was given.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127096704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA implementation of FIR filter with smallest processor 最小处理器FIR滤波器的FPGA实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496716
Chao-Huang Wei, H. Hsiao, S. Tsai
{"title":"FPGA implementation of FIR filter with smallest processor","authors":"Chao-Huang Wei, H. Hsiao, S. Tsai","doi":"10.1109/NEWCAS.2005.1496716","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496716","url":null,"abstract":"Finite impulse response (FIR) filter is the key functional block in the field of digital signal processing. A number of implementations can be found in the public literatures, either by software or hardware solutions. The proposed design is trying to answer the question on whether a solution can be achieved with minimal cost of hardware and software, and how is its performance. In the VLSI implementation, the hardware complexity of the FIR filter is directly proportional to the tap length and the bit-width of input signal. To reduce the hardware cost, this can be solved with iteration calculations by software; therefore, a co-design of hardware and software may produce cost-efficient FIR filters. The key design concept is to build a processor for software processing with minimum hardware resources, without sacrificing the performance of original FIR filter. The proposed design methodology can be considered as an intellectual property (IP) design for FIR filters in system-on-a-chip (SOC) environment.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125985477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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