A novel architecture of a re-configurable parallel DSP processor

Abstract

High performance, flexibility and low power consumption are the most important issues in the current DSP architectures. While the fastest programmable DSP processors are unable to meet the speed requirements of many advanced signal/image processing applications, the ASICS are not always suitable because of their inflexibility. Recently, dynamically re-configurable FPGAs have emerged as high performance flexible programmable hardware to execute highly parallel, computationally intensive functions of image and signal processing applications. However, since the FPGAs are not optimised for any particular application, they can not offer highest possible performance at lowest silicon cost for a given signal processing application. This paper addresses these issues by introducing a novel re-conflgurable parallel DSP processor which eliminates the drawbacks of the FPGAs and ASICs and offers a balance between flexibility, reconfiguration latency and performance.