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Adaptive scheduling for CDMA-based networks-on-chip 基于cdma的片上网络自适应调度
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496682
Manho Kim, Daewook Kim, G. Sobelman
{"title":"Adaptive scheduling for CDMA-based networks-on-chip","authors":"Manho Kim, Daewook Kim, G. Sobelman","doi":"10.1109/NEWCAS.2005.1496682","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496682","url":null,"abstract":"A novel adaptive scheduling algorithm for CDMA-based networks-on-chip is proposed. An orthogonal variable spreading factor (OVSF) code is combined with the dual round robin matching (DRRM) algorithm to obtain efficient usage of orthogonal codewords. The length of codewords is adjusted depending on how many active IP blocks have packets to send at any given time. In addition, pointers are maintained to perform the necessary input and output arbitration. SystemC simulation results demonstrate that our scheduling technique exhibits the fairness property.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113938217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 1.6 GHz digital DLL for optical clock distribution 用于光时钟分配的1.6 GHz数字DLL
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496693
M. Boussaa, Y. Audet
{"title":"A 1.6 GHz digital DLL for optical clock distribution","authors":"M. Boussaa, Y. Audet","doi":"10.1109/NEWCAS.2005.1496693","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496693","url":null,"abstract":"This paper describes the circuit architecture of a digital delay locked loop (DDL)-based clock generator for optical clock distribution. DLL-based clock generators have several advantages over conventional phase lock loop (PLL)-based clock generators, namely their design simplicity and their transferability among CMOS processes. Its architecture is based on a digital phase detector which controls a 6-bit up-down counter. The counter digital output is then converted into an analog signal that generates the control voltage of a delay line. This design is aimed for an on-chip optical clock distribution network where optical receivers are used to transmit the global optical clock signal to local DLL-based clock generators. Hence a frequency multiplier connected at the output of the voltage-controlled delay line allows for a global optical clock operating at lower frequencies which reduces the performance requirements of the optical receiver. Simulation results of the DLL designed in a 0.18/spl mu/m CMOS process are presented. The circuit is able to generate a local clock signal at frequencies ranging from 1.32 to 1.6 GHz.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116246141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integrated low-voltage pulse width modulation circuit using CMOS processes 采用CMOS工艺的集成低压脉宽调制电路
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496722
Yeong-Tsair Lin, Wen-Yaw Chung, Dong-Shiuh Wu, Kang-Shuo Chang, Jiann-Jong Chen
{"title":"Integrated low-voltage pulse width modulation circuit using CMOS processes","authors":"Yeong-Tsair Lin, Wen-Yaw Chung, Dong-Shiuh Wu, Kang-Shuo Chang, Jiann-Jong Chen","doi":"10.1109/NEWCAS.2005.1496722","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496722","url":null,"abstract":"A low-voltage low-power integrated pulse-width-modulation (PWM) circuit using CMOS processes is presented in this paper. The proposed PWM circuit only consists of CMOS transistors and can be implemented with digital CMOS processes without extra internal or/and external passive components. In the proposed circuit, the curve-compensation technique is used to achieve approximately constant frequency operation. This circuit will be useful in low-voltage multimedia circuit, power electronic and telecommunication applications.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123393799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-speed differential frequency-to-voltage converter 高速差动频率-电压转换器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496676
H. Bui, Y. Savaria
{"title":"High-speed differential frequency-to-voltage converter","authors":"H. Bui, Y. Savaria","doi":"10.1109/NEWCAS.2005.1496676","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496676","url":null,"abstract":"This paper proposes a high-speed integrating frequency-to-voltage converter. It overcomes the deficiencies of previous converters by removing 2 of their main bottlenecks: event sequencing using pulses and the use of full-swing signals. By using a single-phase algorithm and circuit-level improvements a frequency-to-voltage converter can operate up to 5 GHz and is able to discriminate between signals whose periods differ by as little as 0.5ps.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A high precision and linearity differential capacitive sensor circuit dedicated to bioparticles detection 一种高精度线性差分电容式传感器电路，专门用于生物颗粒检测
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496669
E. Ghafar-Zadeh, M. Sawan
{"title":"A high precision and linearity differential capacitive sensor circuit dedicated to bioparticles detection","authors":"E. Ghafar-Zadeh, M. Sawan","doi":"10.1109/NEWCAS.2005.1496669","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496669","url":null,"abstract":"The authors presented in this paper an accurate and simple topology circuit dedicated to measure very small percentage of differential capacitance variations. The proposed circuit is based on a charge-based capacitance measurement method (CBCM). The simplified architecture and measurement linearity of the proposed circuit are the two main advantages required to satisfy the design criteria of capacitive sensors array intended for bio-particles detection. The presented simulation results give a minimum measurable differential capacitance of 7 aF in a linearity for 10 fF variation instead of a minimum level of 10 aF in 2 fF variation reported by very recent literature.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126241071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Minimization of delay sensitivity to process induced voltage threshold variations 对过程引起的电压阈值变化的延迟敏感性最小化
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496666
G. Nabaa, F. Najm
{"title":"Minimization of delay sensitivity to process induced voltage threshold variations","authors":"G. Nabaa, F. Najm","doi":"10.1109/NEWCAS.2005.1496666","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496666","url":null,"abstract":"Threshold voltage variations, resulting from underlying process variations, cause variations in circuit delay that can affect the chip timing yield. We study design techniques and optimization strategies that minimize the effects of threshold voltage variations on circuit delay variability. Specifically, we compare different static circuits (classic CMOS, ratioed logic, and transmission gate logic) and dynamic circuits and evaluate their limitations and benefits in terms of delay variability, performance penalty and area overhead. Based on our findings, we also introduce circuit design guidelines and techniques that help mitigate the effects of threshold voltage variations. By reducing delay variability on a per-gate basis, we show how one can build threshold voltage variations-aware gate libraries for use in deep submicron design.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115994957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Detailed routing with integrated static timing analysis applying simulated annealing 详细布线与集成静态时序分析应用模拟退火
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496696
P. Panitz, M. Olbrich, E. Barke
{"title":"Detailed routing with integrated static timing analysis applying simulated annealing","authors":"P. Panitz, M. Olbrich, E. Barke","doi":"10.1109/NEWCAS.2005.1496696","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496696","url":null,"abstract":"The consideration of wiring delays becomes increasingly important. In this paper static timing analysis is incorporated into detailed routing for the first time. The approach applies the placement of routing patterns using simulated annealing. As a result, our router guarantees the fulfillment of timing constraints by construction.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116456142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive equalization of a communication channel in a non-Gaussian noise environment 非高斯噪声环境下通信信道的自适应均衡
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496705
H. Kamel, Wael Badawy
{"title":"Adaptive equalization of a communication channel in a non-Gaussian noise environment","authors":"H. Kamel, Wael Badawy","doi":"10.1109/NEWCAS.2005.1496705","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496705","url":null,"abstract":"The subject of adaptive filters constitutes an important part of statistical signal processing. Adaptive filters are successfully applied in such diverse fields as communications, control, radar, sonar, and biomedical engineering. In this paper we study the use of the particle filter for adaptive equalization of a linear dispersive channel that produces (unknown) distortion. The performance of the adaptive filter is compared to that of least-mean-square (LMS) and recursive-least-square (RLS) algorithms. The main advantage of the particle filter when compared to other algorithms is its robustness when dealing with non-Gaussian noise. The particle filter showed better performance in convergence speed and root-mean-square (rms) error in case of low signal-to-noise ratio.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125298290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementation and error performance evaluation of an iterative decoding algorithm 一种迭代译码算法的实现与错误性能评价
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496661
G. Provost, M. Sawan, C. Cardinal, D. Haccoun
{"title":"Implementation and error performance evaluation of an iterative decoding algorithm","authors":"G. Provost, M. Sawan, C. Cardinal, D. Haccoun","doi":"10.1109/NEWCAS.2005.1496661","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496661","url":null,"abstract":"This paper presents new experimental results about the error correction performance of an iterative threshold decoder at relatively high signal to noise ratio. To accomplish this task, an accelerated characterization platform has been developed. Without this platform, it would take approximately 37.23 years in computational time with a software version of the decoder to get the error correction performances over an extended signal to noise range. An acceleration factor of 4812 is obtained by using the accelerated characterization platform. The platform constitutes a new way for characterizing quickly and efficiently a new error correction algorithm. The acceleration characterization platform has allowed verifying the error correction performance at high SNR which will require a prohibitive computational time on a conventional computer.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127331399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the effect of clock jitter in IF and RF direct sampling systems 中频和射频直接采样系统中时钟抖动的影响
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496679
T. Chalvatzis, E. Gagnon, J. Wight
{"title":"On the effect of clock jitter in IF and RF direct sampling systems","authors":"T. Chalvatzis, E. Gagnon, J. Wight","doi":"10.1109/NEWCAS.2005.1496679","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496679","url":null,"abstract":"The effect of clock jitter on sampling systems is presented. Analytical expressions are derived for the signal-to-noise ratio using the autocorrelation function and its properties. Special focus is given to direct sampling systems for signals with raised cosine power spectral density. Phase noise requirements in CDMA systems are calculated with respect to SNR.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127359920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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