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The rapid prototyping SoC co-design of a proprietary key agreement protocol 专有密钥协议的快速原型SoC协同设计
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496725
R. Glabb, G. Jullien
{"title":"The rapid prototyping SoC co-design of a proprietary key agreement protocol","authors":"R. Glabb, G. Jullien","doi":"10.1109/NEWCAS.2005.1496725","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496725","url":null,"abstract":"In this paper, we present an architecture for the rapid prototyping of a novel SoC co-design system based on a proprietary key negotiation protocol for the purpose of secret key agreement over an insecure channel. We exploit the benefits of co-design in this architecture to facilitate both speed and flexibility, and illustrate specific design strategies that reduced our overall design time and showcase the rapid prototyping methodology. The architecture is centred around a key agreement protocol (protected by NE2 Inc., Calgary), and includes several standard crypto IP blocks based on industry standard protocols which are capable of standalone operation.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127378594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder 一个6位2GSPS内插闪存型CMOS A/D转换器，带缓冲直流参考和1 - 0检测编码器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496704
Yujin Park, Sanghoon Hwang, Minkyu Song
{"title":"A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder","authors":"Yujin Park, Sanghoon Hwang, Minkyu Song","doi":"10.1109/NEWCAS.2005.1496704","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496704","url":null,"abstract":"In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed track-and-hold (T/H), a novel one-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18/spl mu/m CMOS occupies an area of 977/spl mu/m /spl times/ 1040/spl mu/m and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122194709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1 V low-power low-noise DTMOS based class AB opamp 一个1v低功耗低噪声DTMOS的AB类放大器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496678
H. F. Achigui, C. Fayomi, M. Sawan
{"title":"A 1 V low-power low-noise DTMOS based class AB opamp","authors":"H. F. Achigui, C. Fayomi, M. Sawan","doi":"10.1109/NEWCAS.2005.1496678","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496678","url":null,"abstract":"In this paper, the authors described a novel class AB opamp based on dynamic threshold voltage transistors (DTMOS) for low voltage (1-V), low power and low noise applications. The opamp is used to build the front-end receiver part of a near infrared spectroreflectometry (NIRS) device. The opamp has a two-stage configuration; DTMOS pseudo pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class AB output. Experimental measurements from previous designs confirm the usage of a DTMOS device to build a 1-V opamp, using standard 0.18-/spl mu/m CMOS technology. The performed post-layout simulation results show an input referred noise of 107 nV//spl radic/Hz at 1 kHz, and a power consumption of 33.1 /spl mu/W under 5 pF and 10 k/spl Omega/ loads. The dc open loop gain is 60 dB, and a unity frequency of 2.73 MHz. The opamp has a CMRR of 100 dB, and input and output swings of 0.6 V and 0.8 V respectively.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132568395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Shortening SoC design time with new prototyping flow on reconfigurable platform 利用可重构平台上的新原型流程缩短SoC设计时间
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496713
F. Rousseau, A. Sasongko, A. Jerraya
{"title":"Shortening SoC design time with new prototyping flow on reconfigurable platform","authors":"F. Rousseau, A. Sasongko, A. Jerraya","doi":"10.1109/NEWCAS.2005.1496713","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496713","url":null,"abstract":"A modern SoC contains complex hardware components and a huge amount of software. These software parts, including the operating system, become so complex that their validation and debug is not feasible anymore by classical ISS based simulation approaches. Hardware prototypes are built to allow early software development and hardware-software integration. However the development of an application specific prototype takes a lot of time and effort. In this paper, we present an efficient approach for complex SoC prototyping on reconfigurable prototyping platform. This method provides all advantages of hardware prototyping solutions, but it avoids the time and cost required to build an application specific prototype.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134071678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A VHDL-based technique for an accurate estimation of leakage power in digital CMOS circuits 一种基于vhdl的数字CMOS电路漏功率精确估计技术
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496694
A. Nourivand, Chunyan Wang, M. Ahmad
{"title":"A VHDL-based technique for an accurate estimation of leakage power in digital CMOS circuits","authors":"A. Nourivand, Chunyan Wang, M. Ahmad","doi":"10.1109/NEWCAS.2005.1496694","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496694","url":null,"abstract":"Accurate modeling and estimating of the leakage power dissipation in the early stages of the design flow is becoming more important, as the aggressive scaling of transistors results in higher leakage currents. In this work, we present a VHDL-based technique to estimate an accurate leakage power of a design considering the state-dependency of the leakage power. We develop the VHDL models of cells which trace the probability of the static levels of the signals in the course of a simulation. Then, these data are used to calculate the leakage power in the overall design. The leakage power of some benchmark circuits is estimated using the proposed approach and the results are compared with those obtained from SPICE simulation, in order to illustrate the viability of the proposed technique. It is shown that the values of the leakage power obtained by the proposed technique are comparable to those obtained by SPICE, with a reduction of about three orders of magnitude in the simulation time.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122997602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Wavelet-domain image denoising algorithm using series expansion of coefficient P.D.F. in terms of Hermite polynomials 利用系数P.D.F.级数展开的厄米特多项式的小波域图像去噪算法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496680
S. Rahman, M. Ahmad, M. Swamy
{"title":"Wavelet-domain image denoising algorithm using series expansion of coefficient P.D.F. in terms of Hermite polynomials","authors":"S. Rahman, M. Ahmad, M. Swamy","doi":"10.1109/NEWCAS.2005.1496680","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496680","url":null,"abstract":"A new wavelet-domain image denoising algorithm is proposed that uses series expansion of continuous probability density function (pdf) for estimating wavelet coefficient variance field. The expanded pdf is derived using standard normal as weighting function that results the Hermite polynomials in the series. Variance field estimated using the proposed algorithm is used in a minimum mean square error (MMSE) estimator to restore the noisy image wavelet coefficients. Simulation results on standard images show improved performance both in visual quality and in terms of peak signal to noise ratio (PSNR) as compared to other recent image denoising methods.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128923954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
VLSI implementation of bit-parallel word-serial multiplier in GF(2/sup 233/) 位并行字串乘法器在GF(2/sup 233/)中的VLSI实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496706
Wenkai Tang, Huapeng Wu, M. Ahmadi
{"title":"VLSI implementation of bit-parallel word-serial multiplier in GF(2/sup 233/)","authors":"Wenkai Tang, Huapeng Wu, M. Ahmadi","doi":"10.1109/NEWCAS.2005.1496706","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496706","url":null,"abstract":"A bit-parallel word-serial (BPWS) finite field multiplier in GF(2/sup 233/) is proposed in this paper. The complexities are lower than or comparable to those of the previous similar proposals. A VLSI implementation of the BPWS multiplier combined with a bit-parallel squarer is also presented. The fabricated ASIC chip can be used as the finite field arithmetic module on an elliptic curve technique based cryptographic accelerator board and the proposed VLSI design could also be utilized as a design IP core for fast implementation of a cryptographic processor or smart card.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128969145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Universal /spl mu/-power log-domain biquad based on bulk-driven MOSFET 基于块驱动MOSFET的通用/spl μ /功率对数域双路电路
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496702
W. Aly-Mekawi, E. El-Masry
{"title":"Universal /spl mu/-power log-domain biquad based on bulk-driven MOSFET","authors":"W. Aly-Mekawi, E. El-Masry","doi":"10.1109/NEWCAS.2005.1496702","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496702","url":null,"abstract":"A universal continuous-time CMOS biquad filter using novel CMOS bulk driven log-domain integrators is presented. The proposed biquad is simulated by using CMOSP 0.18-/spl mu/m technology parameters offered by the Taiwan Semiconductor Manufacturing Company (TSMC) with a 1.8 V power supply, 10 KHz pole-frequency f/sub o/ unity pole-quality factor Q and bias current of 3.0 nA. The total power dissipation is 20 nW/pole. Also, the sensitivity performances of the filter with respect to device mismatches are simulated in CMOSP 0.18-/spl mu/m SPECTRE using the Monte Carlo analysis.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129143104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A two-mode interpolation error concealment MCI scheme 一种双模插值误差隐藏MCI方案
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496687
Yan Wu, M. Ahmad, M. Swamy
{"title":"A two-mode interpolation error concealment MCI scheme","authors":"Yan Wu, M. Ahmad, M. Swamy","doi":"10.1109/NEWCAS.2005.1496687","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496687","url":null,"abstract":"In this paper, we propose a scheme intended for low bit-rate motion-compensated interpolation to improve the quality of low bit-rate video encoded in conjunction with the frame dropping technique. We develop a two-mode interpolation errors concealment (TMIEC) MCI scheme, which exploits the block-based motion vector field available to the decoder and which can work well in both smooth regions and edge regions. Simulation results demonstrate that, with the help of a gradient estimator, TMIEC results in a better subjective quality and objective quality compared to previously proposed schemes.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115497077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multiple gateway environment for tracking mobile hosts in mobile IP networks 在移动 IP 网络中跟踪移动主机的多网关环境
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496733
P. C. Upadhyay, S. Tiwari
{"title":"Multiple gateway environment for tracking mobile hosts in mobile IP networks","authors":"P. C. Upadhyay, S. Tiwari","doi":"10.1109/NEWCAS.2005.1496733","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496733","url":null,"abstract":"The existing micro mobility protocols, such as cellular IP, HAWAII and hierarchical IP consider that all the base stations within a network are connected to Internet via a gateway. The problem with single gateway network is that in the event of failure of the gateway, packet delivery to the mobile hosts in entire network gets affected. This paper proposes a distance based micro mobility protocol (DB MMP) for locating mobile hosts in IP networks. We incorporate the concept of paging for the idle mobile hosts which, otherwise, put unnecessary burden on the network by sending the signaling messages to the home network after every change in their point of attachment. We assume that each base station is aware of the identification numbers (ID) of its neighboring base stations, and it periodically transmits these IDs in the form of beacon signals, in its coverage area. The proposed scheme completely eliminates the ping pong effect and ensures that in the event of the gateway failure, the mobile hosts attached with only one base station are affected.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126915124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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