A VHDL-based technique for an accurate estimation of leakage power in digital CMOS circuits

Accurate modeling and estimating of the leakage power dissipation in the early stages of the design flow is becoming more important, as the aggressive scaling of transistors results in higher leakage currents. In this work, we present a VHDL-based technique to estimate an accurate leakage power of a design considering the state-dependency of the leakage power. We develop the VHDL models of cells which trace the probability of the static levels of the signals in the course of a simulation. Then, these data are used to calculate the leakage power in the overall design. The leakage power of some benchmark circuits is estimated using the proposed approach and the results are compared with those obtained from SPICE simulation, in order to illustrate the viability of the proposed technique. It is shown that the values of the leakage power obtained by the proposed technique are comparable to those obtained by SPICE, with a reduction of about three orders of magnitude in the simulation time.