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Optimal permutation and spacing for unbiased random, counter, and instruction address buses 无偏随机、计数器和指令地址总线的最佳排列和间隔
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496740
E. Naroska, Shang-Jang Ruan, U. Schwiegelshohn, F. Lai
{"title":"Optimal permutation and spacing for unbiased random, counter, and instruction address buses","authors":"E. Naroska, Shang-Jang Ruan, U. Schwiegelshohn, F. Lai","doi":"10.1109/NEWCAS.2005.1496740","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496740","url":null,"abstract":"The coupling power between adjacent bus wires of nanometer CMOS digital design as well as noise has become an important issue. Thus, it is important to design buses that dissipate less power without sacrificing performance. In this paper, we address this problem for a set of special buses types by simultaneously optimizing wire permutation and spacing. In detail we developed solutions for buses that transmit: (a) unbiased random signals; (b) counter sequences; and (c) processor instruction addresses. Unlike other techniques, our approach solves the permutation and spacing problem optimally. That is, we simultaneously determine wire order and wire spaces. For our experiments, we used instruction address bus traces obtained from 12 SPEC2000 benchmark programs. Compared to a bus layout where the additional wire space is equally distributed, our algorithms can save energy up to 77% for the best case, and 70% on average with only 17 /spl middot/ d/sub min/ additional width, respectively. Compared to encoding approaches, our techniques do not introduce any significant delay to the signals. Hence, the presented approaches are able to reduce power dissipation without notable performance degradation.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125521159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the implementation of a multi-equalizer 关于多均衡器的实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496730
P. Dumais, S. Cormier, F. Gagnon, C. Thibeault
{"title":"On the implementation of a multi-equalizer","authors":"P. Dumais, S. Cormier, F. Gagnon, C. Thibeault","doi":"10.1109/NEWCAS.2005.1496730","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496730","url":null,"abstract":"Nowadays, the use of equalizers in wireless telecommunication systems is facilitated by the evolution of microelectronic. It is now possible to implement more than one equalizer in a programmable circuit. In (Dumais et al., 2004), a multi-equalizer (MEQ) architecture has been presented. The results have shown an improvement in BER performances when the propagation environment is fluctuating. This paper presents the FPGA implementation results of a DFE/LTE multi-equalizer. Multi-equalizing or parallel selection of multiple equalizers outputs is achieved by the definition of a cooperation strategy between filters, an algorithmic validation of the architecture by numerical simulations and a FPGA implementation of the structure.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120988720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A circuit technique to improve phase-locked loop charge pump current matching 一种提高锁相环电荷泵电流匹配的电路技术
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496734
T. Wey
{"title":"A circuit technique to improve phase-locked loop charge pump current matching","authors":"T. Wey","doi":"10.1109/NEWCAS.2005.1496734","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496734","url":null,"abstract":"A transconductor-capacitor (gm-C) circuit is added to the passive loop filter in a charge-pump phase-locked loop (PLL) with digital phase-frequency detector (PFD). The proposed architecture provides an alternative technique for enhancing the performance of the charge pump without high bandwidth active components. The proposed design also increases the order of the loop, enhancing the rejection of low frequency phase noise sources from within the loop.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121337417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Circuit techniques for a 2 GHz AMBA AHB bus 2ghz AMBA AHB总线的电路技术
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496755
A. Landry, Y. Savaria, M. Nekili
{"title":"Circuit techniques for a 2 GHz AMBA AHB bus","authors":"A. Landry, Y. Savaria, M. Nekili","doi":"10.1109/NEWCAS.2005.1496755","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496755","url":null,"abstract":"This paper explores various circuit techniques applicable to design a high-performance full-custom AMBA advanced high-speed bus (AHB). The authors have demonstrated that clock frequencies in excess of 2 GHz are feasible with a 180nm CMOS process from TSMC. This result is obtained by means of proper clocking strategy, aggressive transistor sizing, efficient logic style, and meticulous layout techniques. Feasibility of the proposed bus is supported with details of a run-time reprogrammable VLIW AHB arbiter. Circuit simulations show that this core operates up to 3 GHz.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132680245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparisons of different approaches of realizing IP block configuration in SystemC 在SystemC中实现IP块配置不同方法的比较
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496673
L. Charest, P. Marquet
{"title":"Comparisons of different approaches of realizing IP block configuration in SystemC","authors":"L. Charest, P. Marquet","doi":"10.1109/NEWCAS.2005.1496673","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496673","url":null,"abstract":"SystemC is a quasi open source event driven HDL (hardware description language) reference simulator which was introduced in September 1999 from the OSCI. At first, it meant to be a replacement for VHDL, and, although SystemC can be use for RTL modeling, it is now envisioned by the community as a high level system simulator. SystemC inherits all the properties, methodologies and mechanics of its bases (C and C++) which can be seen as macro-assemblers. This has the positive effect of having a lot of freedom in manners of doing things. This freedom can be beneficial because a given methodology can be chosen accordingly and more appropriately to the situation. On the other hand, freedom has a cost and a designer or IP (intellectual property) provider can lose a lot of time trying to figure out which methodology best fit his needs. In this paper, we establish a comprehensive list of all the different mechanisms for configuring an IP in SystemC. We then compare the different methods and highlight the ones which would best suite, following our opinions, the IP development process and publishing cases.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114856200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design, analysis and measurement of a new dual-band compact hybrid resonator antenna 新型双频紧凑型混合谐振器天线的设计、分析与测量
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496727
Q. Rao, T. Denidni, A. Sebak
{"title":"Design, analysis and measurement of a new dual-band compact hybrid resonator antenna","authors":"Q. Rao, T. Denidni, A. Sebak","doi":"10.1109/NEWCAS.2005.1496727","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496727","url":null,"abstract":"A new dual-band compact hybrid resonator antenna is analyzed, designed and tested in this paper. The analysis is based on electric and magnetic integral equations. In the proposed design, the structure utilizes the combination of a thin circular disk dielectric resonator (DR) and a microstrip fed dogbone slot. By optimizing the structure parameters, the hybrid structure allows not only the DR to resonate at one frequency band but also the dogbone slot to resonate at the other one with the required frequency separation. Based on the above design concept, an antenna prototype dedicated for wireless communication applications centered at 1.9 and 2.45 GHz was successfully designed, fabricated and tested. The instructions give basic guidelines for preparing camera-ready papers for conference proceedings.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
S. M. Rezaul Hasan and Nazmul Ula
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496699
K. Tsai, S. Ruan, Li-wei Chen, F. Lai, E. Naroska
{"title":"S. M. Rezaul Hasan and Nazmul Ula","authors":"K. Tsai, S. Ruan, Li-wei Chen, F. Lai, E. Naroska","doi":"10.1109/NEWCAS.2005.1496699","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496699","url":null,"abstract":"The use of very deep sub-micron (VDSM) technology increases the capacitive and inductive coupling between adjacent wires. It also leads to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of the chip. In this paper, we propose a method to reduce power consumption on buses based on dynamic coding scheme. The proposed method considers capacitive and inductive effects at the same time by using the realistic RLC table and segment invert method. The experimental results show that our approach not only reduces bus power consumption up to 29% but also reduces signal delay up to 34%.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"35 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133247401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
State assignment for low-leakage finite state machines 低泄漏有限状态机的状态分配
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496657
B.F. Tawadros, R. Guindi
{"title":"State assignment for low-leakage finite state machines","authors":"B.F. Tawadros, R. Guindi","doi":"10.1109/NEWCAS.2005.1496657","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496657","url":null,"abstract":"The problem of minimizing both static and dynamic power of synchronous circuits in explored in this paper. We present a new cost function for evaluating the static leakage in finite state machines. New techniques for low leakage (static) and low power (dynamic) state assignment are considered. We show that there are 2/sup n/ state assignments having equal dynamic cost and a different static cost. These techniques were applied to MCNC benchmark circuits and results are given.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133326698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 200 MSPS 10-bit pipelined ADC using digital calibration 采用数字校准的200 MSPS 10位流水线ADC
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496690
D. Morin, Y. Savaria, M. Sawan
{"title":"A 200 MSPS 10-bit pipelined ADC using digital calibration","authors":"D. Morin, Y. Savaria, M. Sawan","doi":"10.1109/NEWCAS.2005.1496690","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496690","url":null,"abstract":"We present in this paper the design and implementation of a 10-bit, 200 Mega samples per second (MSPS) pipelined and digitally calibrated analog-to-digital converter (ADC). The proposed ADC is based on simple topologies of analog building blocks to reach the high sampling rate. On the other hand, the achieved combination of resolution and performances are due to digital calibration, which allows compensating the nonlinearity introduced by the simplified architectures of analog circuits. This ADC was designed and implemented using CMOS 0.18/spl mu/m technology.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"802 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116417561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hardware implementation of large number multiplication by FFT with modular arithmetic 基于模运算的FFT大数乘法的硬件实现
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496674
K. Kalach, J. David
{"title":"Hardware implementation of large number multiplication by FFT with modular arithmetic","authors":"K. Kalach, J. David","doi":"10.1109/NEWCAS.2005.1496674","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496674","url":null,"abstract":"Modular multiplication (MM) for large integers is the foundation of most public-key cryptosystems, specifically RSA, El-Gamal and the elliptic curve cryptosystems. Thus MM algorithms have been studied widely and extensively. Most of works are based on the well known Montgomery multiplication method (MMM) and its variants, which require multiplication in N. Authors have always avoided the fast Fourier transform (FFT) method believing that it is impractical for present system sizes despite its smaller complexity order. In this paper, the authors presented the design and hardware implementation of a FFT-based algorithm using modular arithmetic to efficiently compute very large number multiplications. The algorithm has been implemented in CASM, an intermediate level HDL developed in the laboratory. The target architecture is a FPGA. The algorithm is scalable and can easily be mapped to any operand size. Results show that such algorithm implementation starts to be useful for 4096-bit operands and beyond.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129458012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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