A 200 MSPS 10-bit pipelined ADC using digital calibration

Abstract

We present in this paper the design and implementation of a 10-bit, 200 Mega samples per second (MSPS) pipelined and digitally calibrated analog-to-digital converter (ADC). The proposed ADC is based on simple topologies of analog building blocks to reach the high sampling rate. On the other hand, the achieved combination of resolution and performances are due to digital calibration, which allows compensating the nonlinearity introduced by the simplified architectures of analog circuits. This ADC was designed and implemented using CMOS 0.18/spl mu/m technology.