Optimal permutation and spacing for unbiased random, counter, and instruction address buses

Abstract

The coupling power between adjacent bus wires of nanometer CMOS digital design as well as noise has become an important issue. Thus, it is important to design buses that dissipate less power without sacrificing performance. In this paper, we address this problem for a set of special buses types by simultaneously optimizing wire permutation and spacing. In detail we developed solutions for buses that transmit: (a) unbiased random signals; (b) counter sequences; and (c) processor instruction addresses. Unlike other techniques, our approach solves the permutation and spacing problem optimally. That is, we simultaneously determine wire order and wire spaces. For our experiments, we used instruction address bus traces obtained from 12 SPEC2000 benchmark programs. Compared to a bus layout where the additional wire space is equally distributed, our algorithms can save energy up to 77% for the best case, and 70% on average with only 17 /spl middot/ d/sub min/ additional width, respectively. Compared to encoding approaches, our techniques do not introduce any significant delay to the signals. Hence, the presented approaches are able to reduce power dissipation without notable performance degradation.