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A fully-integrated dual-band VCO with power controlled by body voltage in 130nm CMOS/SOI 全集成双频压控振荡器，功率由130nm CMOS/SOI体电压控制
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496742
L. Geynet, E. de Foucauld, P. Vincent, G. Jacquemod
{"title":"A fully-integrated dual-band VCO with power controlled by body voltage in 130nm CMOS/SOI","authors":"L. Geynet, E. de Foucauld, P. Vincent, G. Jacquemod","doi":"10.1109/NEWCAS.2005.1496742","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496742","url":null,"abstract":"In this paper, a dual-band VCO for wireless applications in CMOS/SOI technology using body voltage to control power consumption and phase noise performance is presented. A new architecture for multi-standards applications is proposed. To our knowledge, this is the first structure using this method to control VCO core current. Two standards are covered by this structure, Bluetooth (2.45GHz) and 802.11a (5.8GHz). The VCO's tuning range can vary from 2.45GHz up to 5.8GHz. The main idea is to use only two MOS varactor to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second one to adjust the oscillation frequency. The realisation of such VCO is possible thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allows changing current and power dissipation in the VCO core. At 200kHz offset, the measured phase noise is -94dBc/Hz and -96dBc/Hz at 5.7GHz and 2.45GHz respectively.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128997359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS direct down-converter with outstanding dynamic range performances 一种动态范围性能优异的CMOS直接下变频器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496718
M. Brandolini, P. Rossi, D. Sanzogni, F. Svelto
{"title":"A CMOS direct down-converter with outstanding dynamic range performances","authors":"M. Brandolini, P. Rossi, D. Sanzogni, F. Svelto","doi":"10.1109/NEWCAS.2005.1496718","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496718","url":null,"abstract":"The mechanisms responsible for second order inter-modulation distortion in a direct down-converter are addressed, giving rise to the following design strategy: the transconductor is degenerated by means of an RC filter with pole equal to the signal bandwidth, an LC filter resonating at RF frequency loads the switching pair and carefully matched load resistors develop voltage gain. Prototypes realized in 0.18/spl mu/m CMOS show: +78dBm IIP2 minimum among 40 samples, +10dBm IIP3, 4nV/VHz input-referred noise density while burning only 4mA from 1.8V.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127568815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of current-mode digital-to-analog converter in hybrid architecture 混合结构中电流型数模转换器的设计
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496715
Chuen-Yau Chen, Chi-Jung Cheng, Chien-Cheng Yu
{"title":"Design of current-mode digital-to-analog converter in hybrid architecture","authors":"Chuen-Yau Chen, Chi-Jung Cheng, Chien-Cheng Yu","doi":"10.1109/NEWCAS.2005.1496715","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496715","url":null,"abstract":"This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-/spl beta/R-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-/spl beta/R-ladder approach that is modified form the R-/spl beta/R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-/spl mu/m 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122068640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Integration of MEMS with a SoC in a microrobot 微型机器人中MEMS与SoC的集成
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496712
Olivier-Don Truong, N. Kaou, S. Martel
{"title":"Integration of MEMS with a SoC in a microrobot","authors":"Olivier-Don Truong, N. Kaou, S. Martel","doi":"10.1109/NEWCAS.2005.1496712","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496712","url":null,"abstract":"This article presents an integration technique for electrostatic motors with a SoC-type microelectronic circuit for design of a miniature robot of size 3 mm /spl times/ 3 mm /spl times/ 3 mm. More precisely, a technique of assembling the parts of a microrobot with the aid of a mould and a compact interconnection technique integrable on a three dimensional structure with the aid of microfabrication techniques.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115534075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current status and trends of CMOS low voltage low power wireless IC designs CMOS低电压低功耗无线集成电路设计的现状与趋势
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496717
T. Tsang, M. El-Gamal, K. Iniewski, K. Townsend, J. Haslett
{"title":"Current status and trends of CMOS low voltage low power wireless IC designs","authors":"T. Tsang, M. El-Gamal, K. Iniewski, K. Townsend, J. Haslett","doi":"10.1109/NEWCAS.2005.1496717","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496717","url":null,"abstract":"This paper surveys recent research on IC designs for wireless applications. Recent advances in device technologies and system architectures are presented. Recent low power wireless systems, both from academia and from industry, are summarized. Circuit design techniques and challenges for low voltage and low power applications are discussed. RF performance and power trade-offs are addressed. Examples of common RF building blocks, e.g. LNA's and VCO's, designed for sub-1 V power supplies are presented.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analysis of continuous-time oversampled sigma-delta modulator with excess loop delay 具有过量环路延迟的连续过采样σ - δ调制器分析
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496708
Quan Li, F. Yuan
{"title":"Analysis of continuous-time oversampled sigma-delta modulator with excess loop delay","authors":"Quan Li, F. Yuan","doi":"10.1109/NEWCAS.2005.1496708","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496708","url":null,"abstract":"This paper presents an efficient circuit-level simulation method for analyzing the effect of the excessive loop delay of continuous-time oversampled sigma-delta modulators (SDMs). The method is based on the sampled-data simulation of linear circuits. The high accuracy is achieved using numerical Laplace inversion. All circuit elements except the quantizer are formulated using a circuit-level approach. The behavior of the quantizer is depicted using a behavior model to avoid the difficulties arising from its harsh nonlinear characteristics. As compared with the modified z-transform approach for analysis of continuous-time over-sampled SDMs, the proposed method is a circuit-level simulation method that offers the efficiency, the accuracy, as well as the ability of handling general nonidealities of circuits. The effectiveness of the proposed method is evaluated using a second-order continuous-time SDM.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123136201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Substrate noise coupling effect characterization for RF CMOS LC VCOs 射频CMOS LC压控振荡器的衬底噪声耦合效应表征
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496758
S. Magierowski, K. Iniewskir, C. Siu
{"title":"Substrate noise coupling effect characterization for RF CMOS LC VCOs","authors":"S. Magierowski, K. Iniewskir, C. Siu","doi":"10.1109/NEWCAS.2005.1496758","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496758","url":null,"abstract":"A generic, mixed-mode 0.18-/spl mu/m substrate is studied using a finite-element device simulator. The isolation properties of the device are extracted for guard ring structures of varying width. The effect of the substrate filtering on randomly switching noise is studied in the context of a 5-GHz CMOS LC-VCO's phase noise performance. Poor high frequency noise damping (/spl sim/ -20 dB) in the substrate due to inductive blocking is responsible for significant degradation of oscillator phase noise in simulation. Measurement results of wideband substrate noise effects on oscillator phase noise are included.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115347577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 6.25Gb/s pipelined half-rate decision feedback equalizer for high speed backplane data communications 用于高速背板数据通信的6.25Gb/s流水线式半速率决策反馈均衡器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496689
J. Chen, T. Kwasniewski
{"title":"A 6.25Gb/s pipelined half-rate decision feedback equalizer for high speed backplane data communications","authors":"J. Chen, T. Kwasniewski","doi":"10.1109/NEWCAS.2005.1496689","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496689","url":null,"abstract":"A pipelined two post-tap half-rate decision feedback equalizer (HRDFE) is proposed. The circuit is composed of equalizing circuit and sampling circuit working at half rate clock, with cross-coupling output of interleaving sampler feedback to the input. A behavioral model of the HRDFE is built in MATLAB to prove the feasibility of the circuit. The design is verified by using 0.18/spl mu/m CMOS process in SPECTRE. Simulation results show eye opening increases at speed up to 6.25Gb/s with data transmitted over a 34\" FR4 backplane. The total power consumption is 8.91 mW with a 1.8V supply.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new topology for power control of high efficiency class-E power amplifier 一种高效率e类功率放大器功率控制的新拓扑
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496744
M. M. Tabrizi, N. Masoumi, S. Aghnout
{"title":"A new topology for power control of high efficiency class-E power amplifier","authors":"M. M. Tabrizi, N. Masoumi, S. Aghnout","doi":"10.1109/NEWCAS.2005.1496744","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496744","url":null,"abstract":"In this paper a new methodology to improve overall efficiency of class E power amplifier is proposed. Power amplifiers are designed to have the maximum efficiency at its highest output power but the efficiency decreases as the output power is reduced. To have more battery life and blocking interference, output power must be controlled due to the distance between the transmitter and the receiver. This new methodology uses optimized circuit topology in power control unit to have small drop in efficiency at low output power. Proposed circuit is simulated with Hspice in 0.25/spl mu/m CMOS technology and ADS lumped model of spiral inductors is used. The results show that the efficiency drop is about 40% when power amplifier is work with its 10% of output power.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130213536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thread scheduling based on low-quality instruction prediction for simultaneous multithreaded processors 基于低质量指令预测的并发多线程处理器线程调度
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496686
H. Homayoun, K. Li, S. Rafatirad
{"title":"Thread scheduling based on low-quality instruction prediction for simultaneous multithreaded processors","authors":"H. Homayoun, K. Li, S. Rafatirad","doi":"10.1109/NEWCAS.2005.1496686","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496686","url":null,"abstract":"A simultaneous multithreaded (SMT) processor is capable of executing instructions from multiple threads in the same cycle. SMT in fact was introduced as a complementary architecture to superscalar to increase the throughput of the processor. Recently, several computer manufacturers have introduced their first generation SMT architecture. SMT permits multiple threads to compete simultaneously for shared resources. An example is the race for the fetch unit which is a critical logic responsible for thread scheduling decisions. When more threads than hardware execution contexts are available, the decision of choosing the best threads to fetch instructions from, will affect the processor's efficiency. In this paper the authors presented a new approach to choose the most useful threads among all available threads while they compete on a shared resource. The quality of instructions was identified based on the time they spend in the instruction queue. Low-quality instructions spend more time in the instruction queue. Accordingly threads with fewer number of low-quality instructions have a higher contribution to the entire processor throughput. In an experimental study, such low-quality instructions in each thread was identified to a maximum of 92% accuracy (average 72%). The authors exploited this to increase the overall processor throughput by giving higher priority to threads with lesser number of low-quality instructions. Overall an average of 11% performance improvement was achieved over the traditional algorithm that schedules threads in a round-robin fashion.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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